Matches 301 - 350 out of 939 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7017133 Designing a semiconductor device layout using polishing regions  
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface...
7016794 Floor plan development electromigration and voltage drop analysis tool  
A method for analyzing electromigration and voltage drop effects in wire segments forming a power-bus grid of an integrated circuit. A floor plan design is created by mapping wire segments to...
7013444 Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same  
A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit...
7013447 Method for converting a planar transistor design to a vertical double gate transistor design  
A method for creating a vertical double-gate transistor design includes providing a planar transistor layout ( 10 ) having a gate layer ( 12 ) overlying an active layer ( 14 ). In one embodiment, a...
7010767 Insertion of repeaters without timing constraints  
A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design...
7007260 Method for fabricating an integrated semiconductor circuit  
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing each of the different wiring forms on...
7003751 Specification of the hierarchy, connectivity, and graphical representation of a circuit design  
Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity...
7003739 Method and apparatus for finding optimal unification substitution for formulas in technology library  
The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a...
7000207 Method of using a Manhattan layout to realize non-Manhattan shaped optical structures  
A system and method for providing the layout of non-Manhattan shaped integrated circuit elements using a Manhattan layout system utilizes a plurality of minimal sized polygons (e.g., rectangles) to...
6996794 Method of designing layout of semiconductor device  
This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the...
6993738 Method for allocating spare cells in auto-place-route blocks  
A method for placing spare cells into an auto-place-route (APR) block of an integrated circuit is disclosed. The list of functional cells to be included in the block is determined along with the...
6993739 Method, structure, and computer program product for implementing high frequency return current paths within electronic packages  
A method, structure and computer program product are provided for implementing high frequency return current paths within electronic packages. Electronic package physical design data is received...
6990647 Variable stage ratio buffer insertion for noise optimization in a logic network  
A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first...
6990646 Hold time error correction method and correction program for integrated circuits  
A hold time error list, having for each hold time error path a hold time error value satisfying plural timing constraints, and more specifically a maximum hold time error value for each of timing...
6986118 Method for controlling semiconductor chips and control apparatus  
The invention relates to a method for operating semiconductor chips, particularly memory chips, which are arranged in groups on modules which are connected to a common data bus wherein each...
6986112 Method of mapping logic failures in an integrated circuit die  
A method of mapping logic failures in an integrated circuit die includes generating a navigation map of test paths for an integrated circuit die, selecting a grid spacing to define a grid map of...
6983235 Method and apparatus for implementing constant latency Z-domain transfer functions using processor elements of variable latency  
In an illustrative embodiment, a desired signal processing transfer function is implemented using a generic pipelined data processor having variable latency followed by a variable latency...
6983443 System and method for placing clock drivers in a standard cell block  
A clock driver placement system and method are provided to place clock drivers in a standard cell block. In accordance with one aspect of the invention, a system is provided for placing clock...
6983431 Simultaneous placement of large and small cells in an electronic circuit  
A method and system for the simultaneous placement of large and small cells in an electronic circuit. A coarse placement using well known methods may provide an initial placement of cells. Cells...
6983440 Shape abstraction mechanism  
A method of simulating a design of an electronic system having multiple layers includes, for each layer, storing a plurality of shape occurrences for the layer. A hierarchy of shape instances...
6983438 Design tool for integrated circuit design  
A method and software relating to determining whether a square die fits into a package without generating drawings. Package parameters are defined and used to calculate die characteristics....
6978433 Method and apparatus for placement of vias  
Method and apparatus for placement of vias is described. More particularly, source power and ground vias are placed in partial response to locations where conductive lines cross over a reserved...
6976235 Region-based voltage drop budgets for low-power design  
A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage...
6973634 IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout  
Some embodiments of the invention provide a region of an integrated-circuit (“IC”) layout that has a plurality of interconnect layers, where at least one particular layer has more than one...
6971076 Method for estimating peak crosstalk noise based on separate crosstalk model  
Crosstalk noise peaks in output signals of nets of an integrated circuit layout design are estimated by first processing the design to estimate resistances and capacitances of the nets. The design...
6968481 Method and device for adapting/tuning signal transit times on line systems or networks between integrated circuits  
A method and a device adapt/tune signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine tuning of differences in transit...
6968525 Implementing method for buffering devices  
An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which...
6968524 Method and apparatus to optimize an integrated circuit design using transistor folding  
A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout...
6961915 Design methodology for dummy lines  
A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy...
6957406 Analytical placement methods with minimum preplaced components  
The invention relates to a method for placing design components of an integrated circuit. A first site is selected. Other sites that are at maximum distances from already used sites may be...
6957413 System and method for specifying integrated circuit probe locations  
A method for including probe locations in an integrated circuit may include specifying probe cells prior to the place and route stage of the design process. The probe cell locations may be...
6954908 Circuit design point selection method and apparatus  
A visualization and data mining technique can be utilized to facilitate analysis of generated sets of design points for an integrated circuit to enable easy and fast understanding of important...
6954919 Semiconductor integrated circuit capable of facilitating layout modification  
A semiconductor integrated circuit includes a variable region to be subjected to a layout modification in conjunction with a change of a circuit component within the variable region; and a fixed...
6950997 Method and system for low noise integrated circuit design  
A method for designing an integrated circuit by a user, including: evaluating noise parameters for design elements of an integrated circuit design; determining if the noise parameters meet noise...
6951002 Design techniques for analyzing integrated circuit device characteristics  
An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved...
6951003 Placing cells of an IC design using partition preconditioning  
A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective...
6948137 Semiconductor integrated device  
A semiconductor integrated device has one signal processing IC and one microcomputer unit (MCU). A few terminals of the IC are connected to the corresponding terminals of the MCU. The terminals of...
6944843 Method for providing a cell-based ASIC device with multiple power supply voltages  
A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M 1 . All fast or...
6941534 Semiconductor device and layout data generation apparatus  
A semiconductor device that facilitates the layout designing of cells and power supply lines. The semiconductor device includes a first power supply line that corresponds to a first power supply...
6941535 Design system of semiconductor integrated circuit element, program, program product, design method of semiconductor integrated circuit element, and semiconductor integrated circuit element  
A design system, a program, a program product and a design method which can easily design a semiconductor integrated circuit element having a decoupling capacitor are provided. In an element region...
6941540 Design method for gate array integrated circuit  
A gate array design method is disclosed for an integrated circuit whose core region is divided into a plurality of areas, each of which includes sequential circuit sites. The method is composed of...
6938232 Floorplanning apparatus deciding floor plan using logic seeds associated with hierarchical blocks  
A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells...
6938233 Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution  
A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of...
6938237 Method, apparatus, and system for hardware design and synthesis  
According to one embodiment of the present invention, a method and system for VLSI hardware design and synthesis is provided in which components provided by a heterogeneous modeling framework are...
6934924 Layout methodology and system for automated place and route  
A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as...
6931612 Design and optimization methods for integrated circuits  
A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of...
6925614 System and method for protecting and integrating silicon intellectual property (IP) in an integrated circuit (IC)  
System and method for integrated circuit (IC) design using silicon intellectual property (IP) libraries that permits the protecting of the designs of circuits in the silicon IP while allowing...
6925026 Semiconductor device adapted for power shutdown and power resumption  
A semiconductor device that achieves high speed and low power consumption that can be used in a real-time system by preventing held data from disappearing at the time of power shutdown and sharply...
6922659 Parameter population of cells of a hierarchical semiconductor structure via file relation  
Parameter population of cells for a hierarchical semiconductor structure via file relation is disclosed. One aspect of the invention is a computerized system that includes a global file of global...
6920624 Methodology of creating an object database from a Gerber file  
A method and apparatus for translating a Gerber data file into a data format usable by vision software through a process whereby a first Gerber data element is selected and examined to determine if...
Matches 301 - 350 out of 939 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >