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7096433 |
Method for power consumption reduction
A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block...
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7096435 |
Method and apparatus for detecting the type of interface to which a peripheral device is connected
A peripheral device is connectable to a computer having one of a first interface and a second interface. The first interface communicates with the peripheral device over a differential data...
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7096445 |
Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long...
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7093215 |
Semiconductor circuit device and circuit simulation method for the same
An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS...
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7093222 |
Power supply wiring method for semiconductor integrated circuit and semiconductor integrated circuit
A power supply wiring method for a semiconductor integrated circuit is disclosed in which power supply provision for logic cells can be performed without invading the wiring area, and a...
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7093225 |
FPGA with hybrid interconnect
An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple...
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7093220 |
Method for generating constrained component placement for integrated circuits and packages
A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a...
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7093217 |
Method and apparatus for determining the optimal fanout across a logic element
A method of determining an optimal transistor fanout. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that...
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7089523 |
Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement
The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of...
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7089519 |
Method and system for performing placement on non Manhattan semiconductor integrated circuits
The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an...
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7089521 |
Method for legalizing the placement of cells in an integrated circuit layout
A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts...
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7086024 |
Methods and apparatus for defining power grid structures having diagonal stripes
A method for defining and producing a power grid structure of an IC having diagonal power and ground stripes. Stripes are placed in a 45° or 135° diagonal direction in relation to an IC layout's...
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7084464 |
Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same
A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for...
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7086025 |
Programmable logic device partitioning method for application specific integrated circuit prototyping
The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by...
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7086015 |
Method of optimizing RTL code for multiplex structures
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an...
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7082595 |
Schematic driven placement method and program product for custom VLSI circuit design
A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition...
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7080343 |
Apparatus and method for selecting a printed circuit board
An apparatus and method for selecting an optimum printed circuit board in terms of its intended use before placement of components on the printed circuit board, information about components to be...
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7076759 |
Methodology for generating a modified view of a circuit layout
A method for generating a modified view of a circuit layout. In a first step, the method includes receiving the circuit layout from a design rule clean database. In a second step, the method...
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7076410 |
Method and apparatus for efficiently viewing a number of selected components using a database editor tool
A method and apparatus for efficiently viewing selected cells using a database editor tool. By using a cell selection list that identifies a number of selected components, the present invention may...
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7076754 |
Functional block design method and apparatus
A functional block design method capable of shortening the period needed for developing functional blocks in compliance with orders. A logic design is prepared for a desired number of memory floor...
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7075179 |
System for implementing a configurable integrated circuit
The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC...
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7073154 |
Apparatus and methods for interconnect zones and associated cells in integrated circuits
An interconnect zone cell resides within an integrated circuit laid out according to a layout. The integrated circuit includes a first circuit block, laid out according to a first minimum feature...
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7072815 |
Relocation of components for post-placement optimization
Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load...
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7073139 |
Method for determining cell body and biasing plate contact locations for embedded dram in SOI
A method for determining contact location for embedded dynamic random access memory (eDRAM) formed in a silicon-on-insulator (SOI) substrate includes reviewing contact design data for an eDRAM...
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7073144 |
Stability metrics for placement to quantify the stability of placement algorithms
A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with...
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7065728 |
Method for placing electrostatic discharge clamps within integrated circuit devices
A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible...
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7065739 |
Pattern correction method of semiconductor device
A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an...
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7065727 |
Optimal simultaneous design and floorplanning of integrated circuit
A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved...
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7062742 |
Routing structure for transceiver core
A routing structure for a transceiver core, the routing structure including a transmitter block design and a receiver block design. The transmitter block design includes two dedicated transmitter...
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7062739 |
Gate reuse methodology for diffused cell-based IP blocks in platform-based silicon products
A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP)...
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7062738 |
Flash memory compiler with flexible configurations
This invention provides a compiler, circuits and a method for generating a flash memory for integrated circuits. This invention provides a flash memory compiler which can generate flexible...
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7062732 |
Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device
To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation...
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7058916 |
Method for automatically sizing and biasing circuits by means of a database
In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell...
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7055119 |
Customized mesh plane, method and computer program product for creating customized mesh planes within electronic packages
A method, apparatus, and computer program product are provided for creating customized mesh planes in electronic packages. Electronic package physical design data is received and signal traces in...
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7051309 |
Implementation of fast data processing with mixed-signal and purely digital 3D-flow processing boars
A system extends the execution time of a pipeline stage to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port...
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7047510 |
Method and system for partitioning an integrated circuit design
A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is...
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7047511 |
Electronic circuit design
A method, system, program product and database for electronic circuit design configured to reduce data storage and computer resource requirements. The invention is binary based and leverages the...
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7036105 |
Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's
Some embodiments of the invention provide an integrated-circuit chip that has a design based on a wiring model that allows at least a particular wiring layer to have more than one preferred wiring...
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7032191 |
Method and architecture for integrated circuit design and manufacture
A system for integrated circuit (IC) design. A structural multi-project wafer (SMPW) comprises a plurality of pre-manufactured and pre-validated functional blocks. The SMPW is pre-fabricated up to...
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7032205 |
Layout and wiring system and recording medium recording the wiring method
It is determined whether a short-run rule can be adapted into a position, where a via cell is parallel and adjacent to a portion of wiring or another via cell. The via cell and the portion of the...
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7028272 |
Reducing cell library development cycle time
An integrated tool which allows layouts for cells to be generated using a combination of synthesis, migration and manual approaches. In an embodiment, a compaction tool of a migration engine/module...
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7028280 |
IC layout buffer insertion method
An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the...
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7024419 |
Network visualization tool utilizing iterative rearrangement of nodes on a grid lattice using gradient method
A visualization system and method for visualization of network data, which is data that represents elements and links between elements. The network data is converted into a data structure, which...
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7024644 |
IC signal path resistance estimation method
Diffusion effects during an IC fabrication process cause actual dimensions of adjacent conductors in an IC to vary from nominal dimensions specified by data defining the IC layout. A computer-aided...
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7020857 |
Method and apparatus for providing noise suppression in a integrated circuit
A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are...
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7020861 |
Latch placement technique for reduced clock signal skew
A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and...
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7018746 |
Method of verifying the placement of sub-resolution assist features in a photomask layout
A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for...
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7017134 |
Automatic floor-planning method capable of shortening floor-plan processing time
An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set...
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7017133 |
Designing a semiconductor device layout using polishing regions
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface...
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7016794 |
Floor plan development electromigration and voltage drop analysis tool
A method for analyzing electromigration and voltage drop effects in wire segments forming a power-bus grid of an integrated circuit. A floor plan design is created by mapping wire segments to...
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