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7398496 |
Unified placer infrastructure
Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer...
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7395516 |
Manufacturing aware design and design aware manufacturing
Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration....
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7392495 |
Method and system for providing hybrid clock distribution
A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the...
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7392168 |
Method of compensating for etch effects in photolithographic processing
A computer system reads data corresponding to an IC layout target layer and performs an etch simulation on the target layer. Etch biases are calculated and the inverse of the etch biases are used...
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7389484 |
Method and apparatus for tiling memories in integrated circuit layout
A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed...
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7389001 |
Reorganizing rectangular layout structures for improved extraction
Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a...
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7386824 |
Determining the placement of semiconductor components on an integrated circuit
Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of...
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7386822 |
Simultaneous timing-driven floorplanning and placement for heterogeneous field programmable gate array
A timing-driven simultaneous placement and floorplanning method based on a multi-layer density system for heterogeneous field programmable gate arrays are disclosed. The field programmable gate...
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7383166 |
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine...
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7383525 |
Design review output apparatus, design review support apparatus, design review system, design review output method, and design review support method
A design-review-output apparatus comprising: an identification unit 14 that, based on circuit information, which correlates and contains target-object identifiers that identify target objects of...
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7376925 |
Method for production of a standard cell arrangement, and apparatus for carrying out the method
A standard cell arrangement can be produced by automatically determining a distance between at least two standard cells in at least one standard cell row. The method also automatically determines...
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7376922 |
Method and apparatus for integrated circuit datapath layout using a vector editor
A vector editor for providing an integrated circuit datapath layout. For one aspect, vectors may be extracted from an integrated circuit design input file using a name-based vector extraction...
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7370304 |
System and method for designing and manufacturing LSI
An LSI designing system includes a memory;, a database configured to store a layout layer definition file, and a control section configured to refer to the database to build up a plurality of...
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7370303 |
Method for determining the arrangement of contact areas on the active top side of a semiconductor chip
In the case of a method according to the invention for determining the arrangement of contact areas on the active top side of a semiconductor chip arranged in or on a housing, firstly semiconductor...
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7370302 |
Partitioning a large design across multiple devices
A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality...
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7366629 |
High frequency module board device
The present invention relates to a high frequency module board device having a high frequency transmitting and receiving circuit for modulating and demodulating a high frequency signal. The high...
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7366649 |
Method for generating and evaluating a table model for circuit simulation
A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured...
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7363597 |
System for placing elements of semiconductor integrated circuit, method of placing elements thereon, and program for placing elements
An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of...
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7360177 |
Method and arrangement providing for implementation granularity using implementation sets
A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality...
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7360192 |
Macrocell, integrated circuit device, and electronic instrument
A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a...
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7356796 |
Method and apparatus to boost high-speed I/O signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces
A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where...
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7353482 |
Routing display facilitating task of removing error
A layout editor apparatus draws line segments constituting a first interconnect line connecting between an output pin and a first input pin so as to draw the first interconnect line as a straight...
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7353479 |
Method for placing probing pad and computer readable recording medium for storing program thereof
A method for placing probing pad and a computer readable recording medium for storing a program thereof are provided. The method is suitable for placing the probing pads in an integrated circuit...
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7353077 |
Methods for optimizing die placement
A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted...
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RE40188 |
System and method for providing an integrated circuit with a unique identification
An integrated circuit identification device (ICID) to be incorporated into an integrated circuit (IC) includes an array of electronic cells in which the magnitude of an output signal of each cell...
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7350173 |
Method and apparatus for placement and routing cells on integrated circuit chips
Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing...
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7346876 |
ASIC having dense mask-programmable portion and related system development method
A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a...
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7340709 |
Method of generating a geometrical rule for germanium integration within CMOS
In a computer-assisted product development system comprising a processor and a storage, a software-implemented method for asserting design rules related to the manufacturability of optoelectronic...
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7340708 |
Method and apparatus for generating layout pattern
A method includes: obtaining process technology definition data related to a process technology of each layer forming a basic cell, from a process technology definition file defining process...
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7340698 |
Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components
A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating...
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7337420 |
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model...
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7337087 |
Circuit analyzing apparatus, circuit analyzing method and circuit analyzing program
A circuit analyzing apparatus for analyzing operation characteristics of a circuit unit in which, on a substrate, circuit devices are arranged, has a part for automatically obtaining a value of a...
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7334209 |
Method and system for generating multiple implementation views of an IC design
A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be...
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7334206 |
Cell builder for different layer stacks
A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of...
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7332917 |
Method for calculating frequency-dependent impedance in an integrated circuit
A method for calculating frequency-dependent impedance in an integrated circuit (IC) having transistors coupled together by a line follows. First, partition the line into a plurality of rectangles...
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7331025 |
Data storage method and data storage device
In a data storage method and device, input data having a pattern are divided into a plurality of fields. A first number of rectangles contained in each field of an original image of the pattern is...
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7331027 |
Method for swapping circuits in a metal-only engineering change
A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books...
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7328419 |
Place and route tool that incorporates a metal-fill mechanism
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of...
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7325224 |
Method and system for increasing product yield by controlling lithography on the basis of electrical speed data
The electrical performance of sub-devices is detected and the corresponding measurement data is used to control a lithography process so as to compensate for any type of process variations during a...
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7318014 |
Bit accurate hardware simulation in system level simulators
A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the...
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7318211 |
Method for physical placement of an integrated circuit based on timing constraints
A method, system, apparatus, and machine-readable medium for physical placement of an integrated circuit based on the timing constraints are provided. The method involves a two-pass physical...
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7312517 |
System-in-package type semiconductor device
A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111...
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7310786 |
IC compaction system
An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal...
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7308668 |
Apparatus and method for implementing an integrated circuit IP core library architecture
An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner...
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7308672 |
Structured algorithmic programming language approach to system design
An algorithmic programming language approach to system design enables design, synthesis, and validation of structured, system-level specifications, and integrates system-level design into the rest...
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7308667 |
LSI physical designing method, program, and apparatus
In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit...
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7305515 |
Performance optimizing compiler for building a compiled DRAM
A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is...
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7305645 |
Method for manufacturing place & route based on 2-D forbidden patterns
The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a...
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7305332 |
System and method for automatic extraction of testing information from a functional specification
A system and method for testing a development device includes extracting multiple parameters of the development device from a product specification for the development device. The parameters being...
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7302660 |
Standard cell, standard cell library, semiconductor device, and placing method of the same
Of a plurality of standard cells in which an N-well region and a P-well region are vertically formed, some standard cells have a border line between the N-well region and the P-well region which is...
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