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7614033 |
Mask data preparation
The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to...
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7610574 |
Method and apparatus for designing fine pattern
Provided are a method and apparatus for designing a fine pattern that can be entirely transferred onto an object. The method includes reading the original data of a fine pattern for exposure. The...
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7607117 |
Representing device layout using tree structure
Methods are described herein for using a tree structure representation for searching selected areas of a programmable device layout in order to determine the existing component configuration of a...
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7603640 |
Multilevel IC floorplanner
To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7596772 |
Methodology and system for setup/hold time characterization of analog IP
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The...
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7594210 |
Timing variation characterization
A method includes grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the...
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7594201 |
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated...
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7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by...
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7590960 |
Placing partitioned circuit designs within iterative implementation flows
A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding...
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7584444 |
System and method for external-memory graph search utilizing edge partitioning
A method and system is provided for generator successor nodes in an external-memory search of a graph having a plurality of nodes and outgoing edges of the plurality of nodes. The method and system...
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7581197 |
Relative positioning of circuit elements in circuit design
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
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7580824 |
Apparatus and methods for modeling power characteristics of electronic circuitry
Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating...
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7577927 |
IC design modeling allowing dimension-dependent rule checking
A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core...
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7571403 |
Circuit verification
In one embodiment, a method for verifying one or more particular properties of a circuit using a learning strategy to determine suitable values of particular verification parameters includes...
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7568179 |
Layout printability optimization method and system
A layout printability optimization method and system is presented that may be used for enhancing the manufacturability and yield of integrated circuits. The method is based on a mathematical...
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7568176 |
Method, system, and computer program product for hierarchical integrated circuit repartitioning
A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more...
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7565635 |
SiP (system in package) design systems and methods
SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module...
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7562325 |
Device to cluster Boolean functions for clock gating
A system for clustering Boolean functions for clock gating according to various exemplary embodiments can include a computer configured to identify at least two small gating groups within a clock...
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7562316 |
Apparatus for power consumption reduction
A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block...
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7555734 |
Processing constraints in computer-aided design for integrated circuits
A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow...
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7555733 |
Hierarchical partitioning
Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several...
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7546567 |
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip
One embodiment of the present invention relates to a process that generates a clock-tree on an integrated circuit (IC) chip. During operation, the process starts by receiving a placement for a chip...
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7546560 |
Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist
A method for optimizing a design of a circuit is disclosed. The method generally includes the steps of (A) identifying a plurality of first flip flops in the design and (B) replacing each of the...
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7546559 |
Method of optimization of clock gating in integrated circuit designs
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for...
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7530045 |
Recursive partitioning based placement for programmable logic devices using non-rectilinear device-cutlines
A method of placing a circuit design on a target device can include subdividing at least a portion of the circuit design into at least a first design-partition and a second design-partition...
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7530035 |
Automatic power grid synthesis method and computer readable recording medium for storing program thereof
An automatic power grid synthesis method and a computer readable recording medium for storing a program thereof for synthesizing power grid in a circuit area are provided. The circuit area has at...
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7526745 |
Method for specification and integration of reusable IP constraints
A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode...
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7519926 |
Semiconductor device and method for designing the same
Disclosed is a method for designing a semiconductor device so as to prevent the device from being broken even when memory circuits are reset. This method is executed using a computer as follows....
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7516433 |
Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long...
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7516423 |
Method and apparatus for designing electronic circuits using optimization
Methods and apparatus for designing electronic circuits, including analog and mixed signal (AMS) circuits, based on an evolutionary optimization approach. In one exemplary embodiment, the...
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7509611 |
Heuristic clustering of circuit elements in a circuit design
An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example,...
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7509595 |
Method and system for enabling energy efficient wireless connectivity
An apparatus and method that enables several different factors associated with the implementation of a particular wireless application to be considered in the design of an energy efficient wireless...
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7509247 |
Electromagnetic solutions for full-chip analysis
A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may...
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7506290 |
Method and system for case-splitting on nodes in a symbolic simulation framework
A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more...
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7506278 |
Method and apparatus for improving multiplexer implementation on integrated circuits
Systems, methods, software, and techniques implementing a multiplexer mapper tool can be used to construct a binary decision diagram (BDD) or related structure representing a series of dependent...
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7496879 |
Concurrent optimization of physical design and operational cycle assignment
Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for...
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7496875 |
Designing method for designing electronic component
A designing method for designing an electronic component aiming at increase in designing efficiency is provided. The designing method has a step of setting a predetermined electrical...
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7480610 |
Software state replay
A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for...
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7478352 |
Method for creating box level groupings of components and connections in a dynamic layout system
A system and method for automatically generating a dynamic layout of a top-level canvas with an internal box layout structure providing a storage element, and a processing element capable of...
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7478351 |
Designing system and method for designing a system LSI
A method for designing a system LSI includes the steps of dividing an algorithmic description (D 1 ) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior...
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7478027 |
Systems, methods, and media for simulation of integrated hardware and software designs
Systems, methods and media for simulation of integrated hardware and software designs are disclosed. More particularly, hardware and/or software for synchronizing cycle timers of an integrated...
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7474011 |
Method for improved single event latch up resistance in an integrated circuit
A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest...
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7472359 |
Behavioral transformations for hardware synthesis and code optimization based on Taylor Expansion Diagrams
A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated...
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7469401 |
Method for using partitioned masks to build a chip
A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of...
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7467368 |
Circuit clustering during placement
A method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to...
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7467367 |
Method and system for clock tree synthesis of an integrated circuit
Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit....
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7467361 |
Pipeline high-level synthesis system and method
According to one embodiment, a pipeline high-level synthesis system receives a high-level description and performs pipeline high-level synthesis for its loop description part to generate a...
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7464364 |
Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device
A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than...
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7464361 |
System and method for asynchronous logic synthesis from high-level synchronous descriptions
A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior.
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