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6721932 Semiconductor integrated circuit device including circuit block having hierarchical structure and method of designing the same  
A semiconductor integrated circuit device of low power consumption having a hierarchical structure is obtained. This semiconductor integrated circuit device employs at least one gated clock...
6721925 Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture  
Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used...
6711719 Method and apparatus for reducing power consumption in VLSI circuit designs  
In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV 2 , where C is the load capacitance being driven by a source cell, F is the switching frequency...
6701499 Effective approximated calculation of smooth functions  
The present invention is directed to a system and method for effective approximation of smooth functions. In an aspect of the present invention, a method for approximating a smooth function for...
6694500 Design circuit pattern for test of semiconductor circuit  
At a level in which high density and miniaturization of wiring of integrated circuits is required to such an extent that optical proximity effect and the correction of optical proximity effect is...
6694492 Method and apparatus for optimizing production yield and operational performance of integrated circuits  
A method and apparatus for optimizing production yield and operational performance of integrated circuits is provided. A nominal operating voltage is used to categorize integrated circuits into a...
6691285 Exponential increments in FET size selection  
A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes...
6691288 Method to debug IKOS method  
A method of debugging an IKOS model. The method includes mapping information contained in either a .pin or .lde file or both into corresponding files which are more user-friendly, readable and...
6687882 Methods and apparatuses for non-equivalence checking of circuits with subspace  
Methods and systems for designing integrated circuits. In one exemplary method, matched registers between the two netlists are determined. The matched registers become cut off points to generate...
6682398 Method for characterizing the planarizing properties of an expendable material combination in a chemical-mechanical polishing process; simulation technique; and polishing technique  
A method for characterizing planarizing properties of a selected expendable material combination in a chemical-mechanical polishing process includes steps of: providing a combination of expendable...
6681376 Integrated scheme for semiconductor device verification  
A method for determining device yield of a semiconductor device design, comprises determining statistics of at least one device parameter from at least two device layer patterns; and calculating...
6681374 Hit-or-jump method and system for embedded testing  
This invention presents a new “Hit-or-Jump” system and method for embedded testing of components of communication systems that can be modeled by communicating extended finite state machines. It...
6678646 Method for implementing a physical design for a dynamically reconfigurable logic circuit  
A method for implementing the physical design for a dynamically reconfigurable logic circuit. The method is carried out using software that forms a physical design flow to take a design...
6678872 Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout  
The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of...
6678873 Method of designing semiconductor integrated circuit device  
In the case of using a database storing therein data on a plurality of circuits which are different in parameters such as circuit scale, memory capacity, number of pins, and operating frequency,...
6668091 3D mesh coding/decoding method  
A progressive coding and decoding method of three-dimensional (3D) mesh data used in the fields of motion picture experts group-4 synthetic and natural hybrid coding (MPEG-4 SNHC), virtual reality...
6668357 Cold clock power reduction  
A multi-mode latch timing circuit has a first set of latches and a second set of latches in each logical path. In a first mode of operation, first and second phase clock signals are provided so...
6668359 Verilog to vital translator  
A method of translating a register transfer level code model includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer...
6668365 Quadratic programming method for eliminating cell overlap and routing congestion in an IC layout  
To help eliminate overlapping cell placements or to reduce routing congestion in an IC layout wherein cells are integer multiples of a standard size cell unit, the layout is organized into an array...
6665849 Method and apparatus for simulating physical fields  
In order to design on-chip interconnect structures in a flexible way, a CAD approach is advocated in three dimensions, describing high frequency effects such as current redistribution due to the...
6665852 Piecewise linear cost propagation for path searching  
The problem of searching for a low cost path from a source location to a target location through a traversable region partitioned into a plurality of tiles is solved using source and target cost...
6665848 Time-memory tradeoff control in counterexample production  
A method for checking a model includes computing a succession of sets of the states of the system, beginning with an initial set of one or more initial states, such that the states in each of the...
6665850 Spanning tree method for K-dimensional space  
The present invention is directed to a spanning tree method for K dimensional space. To address timing driven buffer insertion and clock routing problems clusters of points must be constructed in...
6658636 Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices  
A first and a second netlist of a first and a second function block of a circuit design are correspondingly partitioned into at least a first and a second partition, and a third and a fourth...
6656751 Self test method and device for dynamic voltage screen functionality improvement  
Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being...
6654946 Interscalable interconnect  
The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and...
6654941 Bus I/O placement guidance  
A method for relative pin placement guidance, comprising the steps of (A) placing a plurality of pins to form a pinout in response to a first design, a second design and an attribute and (B)...
6651234 Partition-based decision heuristics for SAT and image computation using SAT and BDDs  
A method for Boolean Satisfiability (SAT). The method comprises using a variable decision heuristic in a SAT algorithm and pruning the search space of SAT using said decision heuristic. The...
6651232 Method and system for progressive clock tree or mesh construction concurrently with physical design  
Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by...
6651235 Scalable, partitioning integrated circuit layout system  
An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a...
6651233 Method and apparatus for measuring congestion in a partitioned region  
One embodiment of the invention is a recursive partitioning method that place circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region...
6634010 ASIC design support system  
An improved ASIC design support system is described. In accordance with the ASIC design support system, it is possible to easily download the latest versions of a necessary library (or libraries)...
6634016 Arrangement for partitioning logic into multiple field programmable gate arrays  
A test system for a design of a network device under test, having multiple design modules, includes multiple field programmable gate arrays configured for performing operations of the respective...
6631509 Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise  
A CAD apparatus includes a determining unit for determining a component order in ascending order of impedance of components for passive components amongst components to be placed on a printed...
6629297 Tracing the change of state of a signal in a functional verification system  
Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of...
6625786 Run-time controller in a functional verification system  
A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each...
6625789 Computer-readable medium for recording interface specifications  
A storage medium readable by a computer for storing a circuit module's interface information, a connection-verifying method for determining whether or not a first circuit module can be connected to...
6618847 Power stabilizer using under-utilized standard cells  
A system and method is provided for placing gate capacitors, or other performance enhancing electrical components, in an under-utilized standard cell region. The present invention is a layout...
6615398 Method for dividing ROM and DDFS using the same method  
The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication...
6611950 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system  
Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin...
6611947 Method for determining the functional equivalence between two circuit models in a distributed computing environment  
This invention determines whether two logic level circuit models have equivalent functionality. The method allows difficult portions of the equivalent functionality check to be partitioned and...
6609235 Method for providing a fill pattern for an integrated circuit design  
A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The...
6609234 Ordering binary decision diagrams used in the formal equivalence verification of digital designs  
A method for ordering input variables in binary decision diagrams is described. Once a plurality of disjoint sets of input variables can be found from the sub-equations of a Boolean function, an...
6601025 Method to partition the physical design of an integrated circuit for electrical simulation  
A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from...
6597362 Integrated circuit having lithographical cell array interconnections  
A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input. The data...
6598210 Semiconductor inspecting system, method and computer  
A semiconductor inspecting method including: extracting a region to be inspected from a design data of a semiconductor device and dividing the region by a lattice to prepare lattice regions;...
6594814 Dynamic pipelining approach for high performance circuit design  
Pipelining is a well-known efficient technique for optimally designing high performance digital circuits. However, conventional pipelining techniques are difficult to pipeline the execution of a...
6591233 Device for and method of simulation, method of setting manufacturing process condition, and recording medium  
A block dividing means ( 2 ) receives an original netlist (D 1 ) defining a circuit to be simulated, selects a to-be-analyzed block specifying a device included in the circuit to be simulated based...
6588000 Method of partitioning large transistor design to facilitate transistor level timing  
A method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical...
6588004 Graphic editor for block diagram level design of circuits  
A method is described herein for designing a circuit using graphic editor software. A graphic design file is generated corresponding to a block diagram created in a graphical user interface...
Matches 351 - 400 out of 607 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >