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Match Document Document Title
7000203 Efficient and comprehensive method to calculate IC package or PCB trace mutual inductance using circular segments and lookup tables  
Disclosed is an improved method of determining mutual inductance of wires in an electronic design. First, the invention selects a pair of wires. Then, the invention adds concentric ring lines to...
6996793 Methods and apparatus for storing and manipulating diagonal interconnect lines of a multidimensional integrated circuit design  
Geometric objects, such as polygons, are defined in a multi-dimensional data space, and are represented by data segments. “N” dimensional hierarchical trees, or “ng” trees, are generated to...
6996788 Hardware-operation description conversion method and program therefor  
A verilog-HDL source at the register-transfer level (RTL) is converted into a programming language executable on computer. Constructed in an analyzing of elements is a data structure corresponding...
6993738 Method for allocating spare cells in auto-place-route blocks  
A method for placing spare cells into an auto-place-route (APR) block of an integrated circuit is disclosed. The list of functional cells to be included in the block is determined along with the...
6990648 Method for identification of sub-optimally placed circuits  
A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without...
6988256 Method and apparatus for pre-computing and using multiple placement cost attributes to quantify the quality of a placement configuration within a partitioned region  
One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC...
6985843 Cell modeling in the design of an integrated circuit  
The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is...
6986119 Method of forming tree structure type circuit, and computer product  
A method of forming a tree structure type circuit includes the steps of dividing a division target region of LSI into a plurality of regions, placing constituent elements as distribution targets in...
6978425 Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners  
A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating...
6976232 Method of designing and making an integrated circuit  
A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated...
6976235 Region-based voltage drop budgets for low-power design  
A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage...
6971080 Placement based design cells injection into an integrated circuit design  
An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a...
6971079 Accuracy of timing analysis using region-based voltage drop budgets  
A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an...
6964029 System and method for partitioning control-dataflow graph representations  
An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the...
6961916 Placement method for integrated circuit design using topo-clustering  
The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered...
6957409 Method and apparatus for generating topological routes for IC layouts using perturbations  
Some embodiments of the invention provide a method for identifying topological routes in a region of an integrated circuit (“IC”) design layout. The method receives a set of nets. Each net in...
6954910 Method and apparatus for producing a circuit description of a design  
A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a...
6952654 Methods for calculating the voltage induced in a device  
Methods are disclosed for calculating the amount of voltage coupled to a device. In some embodiments, the method may comprise identifying a conductor that is coupled to a device, extracting...
6951006 Decomposing IC regions and embedding routes  
Some embodiments of the invention provide a method of identifying routes in a region of an integrated circuit (“IC”) design layout. The region contains at least one net with several routable...
6951002 Design techniques for analyzing integrated circuit device characteristics  
An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved...
6951003 Placing cells of an IC design using partition preconditioning  
A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective...
6944840 Design method and system for achieving a minimum machine cycle for semiconductor integrated circuits  
Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path...
6944843 Method for providing a cell-based ASIC device with multiple power supply voltages  
A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M 1 . All fast or...
6941533 Clock tree synthesis with skew for memory devices  
A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells,...
6938223 Logic circuit having a functionally redundant transistor network  
A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the...
6938231 Method and system for designing circuit layout  
A circuit layout design method capable of an LSI circuit or an electronic printed circuit board free of electromagnetic interference is provided. The layout design method according to the invention...
6938224 Method for modeling noise emitted by digital circuits  
A method of predicting the electromagnetic noise emitted by a digital circuit on an integrated circuit is disclosed. In accordance with the illustrative embodiment, the output of each digital...
6934927 Turn architecture for routing resources in a field programmable gate array  
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery....
6931612 Design and optimization methods for integrated circuits  
A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of...
6928626 System and method for modeling of circuit components  
The present invention relates generally to the field of design automation. More particularly, the present invention relates to a system and method for the modeling of circuit components for use by...
6912705 Method and apparatus for performing operation on physical design data  
A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC...
6912703 Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation  
A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the...
6910198 Method and apparatus for pre-computing and using placement costs within a partitioned region for multiple wiring models  
One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC...
6907588 Congestion estimation for register transfer level code  
A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor...
6907583 Computer aided method of circuit extraction  
A method and apparatus for extracting circuit design information from a pre-existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a...
6907591 Method and apparatus for performing extraction using a neural network  
A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and...
6907594 Wiring route determining apparatus, group determining apparatus, wiring route determining program storing medium and group determining program storing medium  
A wiring route determining apparatus or the like for determining a wiring route for wiring plural blocks dispersedly arranged on a plane in series while taking into account a distance between the...
6904578 System and method for verifying a plurality of states associated with a target circuit  
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within...
6904584 Method and system for placing logic nodes based on an estimated wiring congestion  
A method and system for placing logic nodes based on an estimated wiring congestion are provided. Specifically, under the present invention, relative probabilities for potential implementations of...
6900540 Simulating diagonal wiring directions using Manhattan directional wires  
An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections,...
6895524 Circuit reduction technique for improving clock net analysis performance  
A method for reducing a transistor circuit netlist for clock network timing verification is provided. Further, a simulation tool that reduces a transistor circuit netlist such that nonlinear...
6892366 Method and apparatus for performing extraction using a model trained with Bayesian inference via a Monte Carlo method  
A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of...
6886145 Reducing verification time for integrated circuit design including scan circuits  
A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality...
6886144 Logic verification method for semiconductor device  
In designing a semiconductor device, a method of verifying an upper-hierarchy logic including a lower-hierarchy logic. First, a first verification logic having an output terminal, which is...
6883155 Macro design techniques to accommodate chip level wiring and circuit placement across the macro  
Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may...
6883154 LP method and apparatus for identifying route propagations  
Some embodiments provide an LP method that identifies route propagations. In some embodiments, this method is used by a router that hierarchically defines routes for nets within a region of a...
6883152 Voltage island chip implementation  
A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of...
6876961 Electronic system modeling using actual and approximated system properties  
A technique is provided for use in computerized modeling of an electronic system. The technique bases simulation of the system's operation (e.g., timing operation) upon both actual physical...
6877120 Method of acquiring scan chain reorder information, and computer product  
The method of acquiring scan chain reorder information performs scan composition on the basis of a net list before the scan composition and acquires two or more pieces of information from a group...
6871329 Design system of integrated circuit and its design method and program  
A circuit modification portion modifies circuit information of an integrated circuit depending on a result of a timing test at a timing test portion to presume delay information at a delay...
Matches 251 - 300 out of 608 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >