Patents in Class 716/7

Matches 51 - 100 out of 609

Match	Document	Document Title
51	7467367	Method and system for clock tree synthesis of an integrated circuit Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit....
52	7467368	Circuit clustering during placement A method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to...
53	7464361	System and method for asynchronous logic synthesis from high-level synchronous descriptions A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior.
54	7464364	Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than...
55	7461360	Validating very large network simulation results A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws...
56	7458050	Methods to cluster boolean functions for clock gating A method to cluster Boolean functions for clock gating according to various exemplary embodiments can include identifying at least two small gating groups within a clock tree representative of an...
57	7454732	Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a...
58	7454727	Method and Apparatus for Solving Sequential Constraints Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior....
59	7451416	Method and system for designing an electronic circuit A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an...
60	7451430	Apparatus and method for generating transistor model In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion...
61	7448003	Signal flow driven circuit analysis and partitioning technique A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital...
62	7448015	Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive...
63	7444275	Multi-variable polynomial modeling techniques for use in integrated circuit design Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data...
64	7444277	Facilitating simulation of a model within a distributed environment Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on...
65	7437691	VLSI artwork legalization for hierarchical designs with multiple grid constraints A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid...
66	7434199	Dense OPC A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a...
67	7434185	Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files...
68	7428477	Simulation of electrical circuits A method, computer program product, and apparatus for simulating circuits. The method comprises modeling a circuit with an appropriate system of equations, partitioning a time interval on which the...
69	7428715	Hole query for functional coverage analysis Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set...
70	7421669	Using constraints in design verification A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate...
71	7421671	Graph pruning scheme for sensitivity analysis with partitions A method of analyzing a circuit simulation comprising pruning a signal flow graph. Pruning the signal flow graph includes selecting a current vertex from a multiple input vertices in the signal...
72	7418688	Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the...
73	7404159	Critical area computation of composite fault mechanisms using Voronoi diagrams Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi...
74	7404168	Detailed placer for optimizing high density cell placement in a linear runtime A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to...
75	7404169	Clock signal networks for structured ASIC devices Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor...
76	7404172	Method for the synthesis of VLSI systems based on data-driven decomposition The present invention is a systematic and data-driven-decomposition (DDD) method and apparatus for use in VLSI synthesis. The invention decomposes a high level program circuit description into a...
77	7401310	Integrated circuit design with cell-based macros A method for designing integrated circuits may include custom designing, at the transistor level, individual cells to be incorporated into cell-based macros. A macro-level function of an integrated...
78	7401319	Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational...
79	7392494	Clustering circuit paths in electronic circuit design Techniques are disclosed for clustering circuit paths in an electronic design automation process for use in improving the timing characteristics of the overall circuit design. Circuit paths...
80	7389484	Method and apparatus for tiling memories in integrated circuit layout A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed...
81	7386823	Rule-based schematic diagram generator A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and...
82	7386776	System for testing digital components In order to test digital modules with functional elements, these are divided into test units ( 3 ) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of...
83	7386821	Primitive cell method for front end physical design A method for forming an integrated circuit ( 280 ) comprises accessing ( 282 ) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code...
84	7383524	Structure for storing a plurality of sub-networks Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
85	7380184	Sequential scan technique providing enhanced fault coverage in an integrated circuit According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation...
86	7380229	Automatic generation of correct minimal clocking constraints for a semiconductor product A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor...
87	7380226	Systems, methods, and apparatus to perform logic synthesis preserving high-level specification A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one...
88	7376921	Methods for tiling integrated circuit designs Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then...
89	7373631	Methods of producing application-specific integrated circuit equivalents of programmable logic Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively...
90	7370308	Integrated circuit analysis method and program product A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches...
91	7370291	Method for mapping logic design memory into physical memory devices of a programmable logic device A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating...
92	7370302	Partitioning a large design across multiple devices A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality...
93	7366649	Method for generating and evaluating a table model for circuit simulation A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured...
94	7363596	Methods for storing and naming static library cells for lookup by logic synthesis and the like A method is provided for creating and using a library of known logic elements for facilitating the design of equivalent FPGA, structured ASIC, or other integrated circuits. Each cell in the library...
95	7360177	Method and arrangement providing for implementation granularity using implementation sets A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality...
96	7356797	Logic transformation and gate placement to avoid routing congestion A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple...
97	7356785	Optimizing IC clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first...
98	7356784	Integrated synthesis placement and routing for integrated circuits A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or...
99	7353472	System and method for testing pattern sensitive algorithms for semiconductor design A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into...
100	7350172	Reporting of aspects and partitioning of automatically generated code according to a partitioning scheme A method and system are described for generating a performance prediction report to assist finalizing a partitioning scheme of a block diagram model. Providing a user-defined partitioning scheme...

Matches 51 - 100 out of 609

< 1 2 3 4 5 6 7 8 9 10 11 12 13 >