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7620921 |
IC chip at-functional-speed testing with process coverage evaluation
Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design;...
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7620920 |
Time separated signals
Systems, methods, and other embodiments associated with time separated signals are described. One system embodiment includes a delay circuit, two or more sets of interconnects, and a clocked...
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7620857 |
Controllable delay device
Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit...
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7617466 |
Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device
A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths. The hazard check device includes a means for equivalent conversion...
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7617465 |
Method and mechanism for performing latch-up check on an IC design
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then...
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7614024 |
Method to implement metal fill during integrated circuit design and layout
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known...
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7614023 |
System for estimating a terminal capacitance and for characterizing a circuit
A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit includes providing first and second capacitance values associated with an upper and lower...
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7610567 |
Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs
Methods and systems automate an approach to provide a way to convert a circuit design from a synchronous representation to an asynchronous representation without any designer or user interaction or...
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7610566 |
Method and apparatus for function decomposition
Some embodiments provide a method of performing circuit synthesis that receives a design that has a function with several inputs. The method identifies a set of early arriving inputs of the...
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7607116 |
Method and apparatus for verifying system-on-chip model
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification...
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7607115 |
System, method and computer program product for timing-independent sequential equivalence verification
A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to...
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7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry
Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first...
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7600206 |
Method of estimating the signal delay in a VLSI circuit
A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI...
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7600205 |
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method
The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with...
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7599826 |
System and method for generating various simulation conditions for simulation analysis
A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module ( 301 ) for generating an N-bit binary sequence...
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7596775 |
Method for determining a standard cell for IC design
IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index)...
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7596774 |
Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
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7596772 |
Methodology and system for setup/hold time characterization of analog IP
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The...
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7594211 |
Methods and apparatuses for reset conditioning in integrated circuits
Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred...
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7594210 |
Timing variation characterization
A method includes grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the...
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7594209 |
Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis
A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is...
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7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been...
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7594202 |
Optimization of circuit designs using a continuous spectrum of library cells
The present invention comprises a method of optimizing a circuit design having a plurality of library cells. In one embodiment, the method includes the steps of providing a plurality of logically...
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7590964 |
Method and system for automatic generation of processor datapaths using instruction set architecture implementing means
Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for...
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7590961 |
Integrated circuit with signal skew adjusting cell selected from cell library
An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal...
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7590958 |
Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities
A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing...
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7590957 |
Method and apparatus for fixing best case hold time violations in an integrated circuit design
The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to...
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7590953 |
Static timing analysis and dynamic simulation for custom and ASIC designs
A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the...
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7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets
The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing...
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7587699 |
Automated system for designing and developing field programmable gate arrays
An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is...
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7587696 |
Semiconductor device, layout method and apparatus and program
A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is...
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7587693 |
Apparatus and method of delay calculation for structured ASIC
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a...
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7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction
One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which...
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7587690 |
Method and system for global coverage analysis
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and...
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7587689 |
Method of supporting wiring design, supporting apparatus using the method, and computer-readable recording medium
A method of supporting an optimum wiring design of a linear structure, includes steps of providing a finite element model of both of the linear structure and a support member which supports the...
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7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a...
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7584443 |
Clock domain conflict analysis for timing graphs
The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while...
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7584442 |
Method and apparatus for generating memory models and timing database
A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each...
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7584441 |
Method for generating optimized constraint systems for retimable digital designs
A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization...
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7584439 |
Cell modeling for integrated circuit design with characterization of upstream driver strength
A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A...
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7584438 |
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout...
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7581201 |
System and method for sign-off timing closure of a VLSI chip
A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in...
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7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and...
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7577933 |
Timing driven pin assignment
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design...
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7577930 |
Method and apparatus for analyzing integrated circuit operations
A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a...
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7577928 |
Verification of an extracted timing model file
A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer...
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7574687 |
Method and system to optimize timing margin in a system in package module
In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are...
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7574344 |
Static timing based IR drop analysis
A method for determining a maximum IR drop on a power grid of a circuit is disclosed. The method includes dividing a reference timing signal into multiple bins. Each one of the bins having a...
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7571414 |
Multi-project system-on-chip and its method
A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral...
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7571407 |
Semiconductor integrated circuit and method of testing delay thereof
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
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