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7350168 |
System, method and computer program product for equivalence checking between designs with sequential differences
A system, method and computer program product are provided for equivalency checking between a first design and a second design having sequential differences. To accomplish the equivalency checking,...
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7350171 |
Efficient statistical timing analysis of circuits
Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended...
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7346873 |
Clocktree tuning shims and shim tuning method
A digital storage medium for storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit. The electronic data implements a...
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7346867 |
Method for estimating propagation noise based on effective capacitance in an integrated circuit chip
A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise...
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7346874 |
Parametric timing analysis
Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their...
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7346880 |
Differential clock ganging
Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect...
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7346861 |
Programmable logic devices with two-phase latch circuitry
Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least...
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7346872 |
Functional timing analysis for characterization of virtual component blocks
A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and...
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7346860 |
User non-volatile memory interface megafunction
An interface for a programmable logic device having a non-volatile memory where a portion of the non-volatile memory is user accessible is provided. A megafunction provides the electronic circuit...
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7343576 |
Conductor trace design to reduce common mode cross-talk and timing skew
A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns...
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7343571 |
Simulation model for a semiconductor device describing a quasi-static density of a carrier as a non-quasi-static model
There is disclosed a simulation model for designing a semiconductor device, comprising adding at least a part of a difference between a density of a carrier described in a quasi-static manner with...
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7343574 |
Method of supporting wiring design, supporting apparatus using the method, and computer-readable recording medium
A supporting apparatus includes a first setting unit which sets an initial shape of the linear structure, a providing unit which provides a finite element model of the linear structure, a second...
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7343572 |
Vector interface to shared memory in simulating a circuit design
A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second...
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7343570 |
Methods, systems, and media to improve manufacturability of semiconductor devices
Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable...
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7340702 |
Method and apparatus for induction proof
Inductive proof can be an improvement to bounded verification. Forward and backward inductive proof methods are disclosed, which can improve the process of verifying properties of circuit designs....
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7340694 |
Method and system for reduction of XOR/XNOR subexpressions in structural design representations
A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the...
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7340707 |
Automatic tuning of signal timing
A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various...
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7340695 |
Reformulation of the finite-difference time-domain algorithm for hardware-based accelerators
A hardware-based acceleration platform for computational electromagnetic algorithms, specifically the finite-difference time-domain (“FDTD”) method, comprises reformulating the FDTD algorithm...
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7340698 |
Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components
A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating...
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7340710 |
Integrated circuit binning and layout design system
A method for binning and layout of an integrated circuit design which includes providing a table setting forth predefined widths of signal wires and corresponding spacing to shield wires,...
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7337087 |
Circuit analyzing apparatus, circuit analyzing method and circuit analyzing program
A circuit analyzing apparatus for analyzing operation characteristics of a circuit unit in which, on a substrate, circuit devices are arranged, has a part for automatically obtaining a value of a...
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7337419 |
Crosstalk noise reduction circuit and method
In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that...
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7334203 |
RaceCheck: a race logic analyzer program for digital integrated circuits
Techniques for performing static and dynamic race logic analysis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language)...
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7334204 |
System for avoiding false path pessimism in estimating net delay for an integrated circuit design
A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output,...
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7331029 |
Method and system for enhancing circuit design process
A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the...
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7331024 |
Power-consumption calculation method and apparatus
An apparatus for calculating power consumption includes a behavioral synthesis unit for generating a clock-level description by behavioral synthesis of an algorithm description; a clock-level...
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7331021 |
Fast/slow state machine latch
A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present...
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7328415 |
Modeling blocks of an integrated circuit for timing verification
An integrated circuit may be divided into blocks and analyzed using a modeling algorithm which facilitates the concurrent analysis of a plurality of blocks forming an integrated circuit. In some...
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7328416 |
Method and system for timing modeling for custom circuit blocks
A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output...
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7328143 |
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened...
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7325215 |
Timing violation debugging inside place and route tool
A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route...
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7325212 |
Method and device for electronic circuit designing, and computer product
Noise related to a part of electronic circuits that are to be designed is computed. If the computed noise exceeds a limiting value, parameters of the electronic circuits are modified by using a...
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7324914 |
Timing closure for system on a chip using voltage drop based standard delay formats
A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test,...
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7324932 |
Virtual test environment
A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing...
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7325210 |
Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that...
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7325211 |
Clock skew modelling using delay stamping
A method for determining clock skew to avoid hold time violations is provided. The method includes obtaining a total delay to a source by adding a first delay associated with each of the delay...
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7322018 |
Method and apparatus for computing feature density of a chip layout
One embodiment of the present invention provides a system that computes feature density for a number of areas within a layout by moving a window across the layout, which allows the system to...
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7320090 |
Methods, systems, and media for generating a regression suite database
Methods, systems and media for generating an improved regression suite by applying harvesting models and/or regression algorithms to tests utilized in verification of a system are disclosed. In one...
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7320118 |
Delay analysis device, delay analysis method, and computer product
A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a...
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7319947 |
Method and apparatus for performing distributed simulation utilizing a simulation backplane
A method and apparatus for performing distributed simulation is presented. According to an embodiment of the present invention, simulators are interfaced to a simulation backplane via...
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7320117 |
Design method for semiconductor integrated circuit device using path isolation
A design method for a semiconductor integrated circuit device wherein for a path having a signal arrival time longer than a desired signal arrival time, and among multiple paths in the...
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7318209 |
Pulse-width limited chip clock design
A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the...
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7318074 |
System and method for achieving deferred invalidation consistency
In a system having a plurality of caches, a method for maintaining cached objects includes storing an object in a plurality of caches. In response to a request to update the object, a future...
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7318208 |
Method for circuit sensitivity driven parasitic extraction
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing...
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7315993 |
Verification of RRAM tiling netlist
The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part”...
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7315802 |
Methods of logic reduction in electrical circuits utilizing fault simulation
Methods of reducing the amount of logic in a digital circuit without affecting the functionality of the circuit. A circuit description and one or more test patterns are supplied to a fault...
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7313770 |
MOSFET modeling for IC design accurate for high frequencies
The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a...
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7310792 |
Method and system for modeling variation of circuit parameters in delay calculation for timing analysis
A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in...
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7308659 |
Apparatus and method for RTL modeling of a register
The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are...
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7308664 |
Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing
A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay...
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