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7464355 Timing analyzing method and apparatus for semiconductor integrated circuit  
A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition. The best-case...
7464359 Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure  
Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed...
7464349 Method and system or generating a current source model of a gate  
Aspects for generating a current source model of a gate include extracting the current source model of the gate. The current source model of the gate is a function of time and output voltage of the...
7464353 Method and apparatus for generating technology independent delays  
A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication...
7464354 Method and apparatus for performing temporal checking  
An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During...
7461360 Validating very large network simulation results  
A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws...
7458046 Estimating the difficulty level of a formal verification problem  
Estimating the difficulty level of a verification problem includes receiving input comprising a design and properties that may be verified on the design. Verification processes are performed for...
7458048 Computer program product for verification of digital designs using case-splitting via constrained internal signals  
A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design,...
7457738 Method for decoding instruction in architectural simulator  
In order to decode a simulation instruction in accordance with the present invention, a new decoding program is generated, which includes flat-type decoding codes for at least one of the...
7458049 Aggregate sensitivity for statistical static timing analysis  
A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution...
7458039 Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit  
An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits ( 10 a - c ). The stream processing circuits ( 10 a - c ) have control parameter inputs for...
7454735 ASIC clock floor planning method and structure  
A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together...
7454729 Method and system for validating testbench  
A method for validating timing violations in a testbench is provided. The method includes obtaining the timing requirements for a design under test from a first file. The timing requirements for...
7454730 Repeater insertion for concurrent setup time and hold time violations  
A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within...
7454719 System and method for calculating effective capacitance for timing analysis  
A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an...
7454731 Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques  
Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a...
7453289 Transmission circuit, CMOS semiconductor device, and design method thereof  
A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a...
7451416 Method and system for designing an electronic circuit  
A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an...
7451417 Timing annotation accuracy through the use of static timing analysis tools  
A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional...
7451418 Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size  
Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated...
7451412 Speeding up timing analysis by reusing delays computed for isomorphic subcircuits  
One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block...
7451413 Methods of minimizing leakage current by analyzing post layout information and associated threshold voltage and leakage current  
Methods, systems and computer program products for automatically minimizing leakage current in a circuit design can include post layout delay information of a circuit that meets timing limits is...
7448009 Method of leakage optimization in integrated circuit design  
This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells,...
7448003 Signal flow driven circuit analysis and partitioning technique  
A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital...
7448005 Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver  
A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial...
7448011 Layout method of semiconductor integrated circuit and cell frame standardization program  
Cells with the same logic and similar driving capability among cells arranged on a substrate of a semiconductor integrated circuit are made into a format comprising terminals at the same position...
7448015 Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation  
A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive...
7448008 Method, system, and program product for automated verification of gating logic using formal verification  
Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is...
7448006 Logic-synthesis method and logic synthesizer  
The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes...
7448007 Slew constrained minimum cost buffering  
A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a...
7444608 Method and system for evaluating timing in an integrated circuit  
Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the...
7444600 System and method for circuit noise analysis  
Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic...
7444604 Apparatus and methods for simulation of electronic circuitry  
A system for analyzing a model of an electronic circuit, which includes at least one non-linear circuit element, includes a computer. The computer replaces the non-linear circuit element with a...
7444574 Stimulus extraction and sequence generation for an electric device under test  
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from...
7444606 Method for designing semiconductor integrated circuit, semiconductor integrated circuit and program for designing same  
In lower hierarchy design in which a plurality of circuit blocks are independently designed, a reset adjustment circuit propagating deactivation transition of a reset signal to flip-flops in...
7444610 Visualizing hardware cost in high level modeling systems  
Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The...
7444605 Generating a base curve database to reduce storage cost  
An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing...
7444602 Method of generating ASIC design database  
When a function design has been carried out by an RTL description using an HDL language, a CPU of an integrated circuit design support apparatus writes data such as a simulation time, a layout...
7444607 Method for correcting timing error when designing semiconductor integrated circuit  
A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching...
7441214 Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media  
In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed...
7441217 Method and apparatus for creating simplified false-path description on false path, and computer product  
An apparatus for creating a simplified false-path description on a false path among paths in a target circuit extracts, from descriptions on the paths, a target path description on a target path....
7441211 Gate-length biasing for digital circuit optimization  
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a...
7437697 System and method of criticality prediction in statistical timing analysis  
A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being...
7437694 System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design  
A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is...
7437696 Method and device for determining the time response of a digital circuit  
A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock...
7437695 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices  
A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy...
7434187 Method and apparatus to estimate delay for logic circuit optimization  
Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the...
7434181 Debugger of an electronic circuit manufactured based on a program in hardware description language  
A device for debugging an electronic circuit manufactured based on an initial program in hardware description language comprising an instrumentation unit capable of determining a first additional...
7434183 Method and system for validating a hierarchical simulation database  
System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing...
7430728 Method and apparatus for selecting programmable interconnects to reduce clock skew  
A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock...
Matches 201 - 250 out of 1637 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >