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7587693 |
Apparatus and method of delay calculation for structured ASIC
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a...
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7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets
The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing...
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7587690 |
Method and system for global coverage analysis
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and...
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7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a...
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7584442 |
Method and apparatus for generating memory models and timing database
A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each...
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7584438 |
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout...
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7584441 |
Method for generating optimized constraint systems for retimable digital designs
A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization...
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7584439 |
Cell modeling for integrated circuit design with characterization of upstream driver strength
A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A...
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7584443 |
Clock domain conflict analysis for timing graphs
The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while...
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7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and...
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7581201 |
System and method for sign-off timing closure of a VLSI chip
A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in...
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7577933 |
Timing driven pin assignment
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design...
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7577930 |
Method and apparatus for analyzing integrated circuit operations
A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a...
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7577928 |
Verification of an extracted timing model file
A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer...
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7574344 |
Static timing based IR drop analysis
A method for determining a maximum IR drop on a power grid of a circuit is disclosed. The method includes dividing a reference timing signal into multiple bins. Each one of the bins having a...
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7574687 |
Method and system to optimize timing margin in a system in package module
In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are...
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7571414 |
Multi-project system-on-chip and its method
A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral...
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7571404 |
Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise
A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network...
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7571402 |
Scan chain modification for reduced leakage
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
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7571406 |
Clock tree adjustable buffer
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of...
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7571405 |
Electrical design rule checking expert traverser system
Method and apparatus for rule checking systems that validate an electronic design is disclosed. Generally, information is extracted from a plurality of nodes in a netlist and stored for a set of...
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7571407 |
Semiconductor integrated circuit and method of testing delay thereof
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
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7571401 |
Calculating distortion summaries for circuit distortion analysis
Methods for analyzing circuit distortion based on contributions from separate circuit elements are presented. Local approximations that do not require high-order derivatives of device models are...
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7571400 |
Chip design verifying and chip testing apparatus and method
A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a...
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7567893 |
Clock simulation system and method
A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock...
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7568175 |
Ramptime propagation on designs with cycles
A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime...
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7568006 |
e-Business on-demand for design automation tools
Methods, apparatus and articles of manufacture are disclosed for a design automation application to evaluate a design automation task using an on-demand computer network. A requesting entity...
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7562330 |
Budgeting global constraints on local constraints in an autorouter
Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a...
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7562335 |
Semiconductor device and method of testing the same
An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of...
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7562324 |
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew...
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7562321 |
Method and apparatus for structured ASIC test point insertion
Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the...
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7559041 |
Method and apparatus for designing semiconductor integrated circuit
A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit...
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7559040 |
Optimization of combinational logic synthesis through clock latency scheduling
In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in...
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7557626 |
Systems and methods of reducing power consumption of digital integrated circuits
There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system...
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7557606 |
Synchronization of data signals and clock signals for programmable logic devices
Techniques for synchronizing data signals and clock signals of a programmable logic device (PLD) are provided. In one example, a method includes preparing an initial configuration of the PLD...
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7559045 |
Database-aided circuit design system and method therefor
A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage...
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7555416 |
Efficient transistor-level circuit simulation
Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.
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7555740 |
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis
Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an...
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7555737 |
Auxiliary method for circuit design
For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is...
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7555417 |
Selectively reducing the number of cell evaluations in a hardware simulation
An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the...
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7552412 |
Integrated circuit (IC) chip design method, program product and system
A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance...
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7552409 |
Engineering change order process optimization
A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in...
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7552413 |
System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model
A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design...
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7552040 |
Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times....
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7549134 |
Method and system for performing crosstalk analysis
Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as...
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7549135 |
Design methodology of guard ring design resistance optimization for latchup prevention
A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS...
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7549069 |
Estimating software power consumption
Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by...
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7549139 |
Tuning programmable logic devices for low-power design implementation
A method of operating a programmable logic device includes the steps of using a full V DD supply voltage to operate a first set of active blocks of the programmable logic device, and using a...
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7549137 |
Latch placement for high performance and low power circuits
A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a...
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7546231 |
Method of simulating semiconductor integrated circuit
A method and computer program for simulating a semiconductor integrated circuit is disclosed, in which a voltage coefficient of resistance according to a variation of width or length of a resistor...
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