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7131082 |
Delay distribution calculation method, circuit evaluation method and false path extraction method
Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving...
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7131088 |
Reliability based characterization using bisection
In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and...
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7131090 |
Clocked gating based on measured performance
A method of determining a forced gating function for at least one of a plurality of clocked state-holding elements. The forced gating function compares the input and output of said at least one...
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7131092 |
Clock gating circuit
Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a...
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7131081 |
Scalable scan-path test point insertion technique
A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately...
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7131091 |
Generating fast logic simulation models for a PLD design description
Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is...
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7131089 |
Computer program for programming an integrated circuit speed capability indicator
A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path comprises a plurality of logic functions...
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7131087 |
Multi-cycle path analyzing method
An analysis of a circuit to be analyzed is made in correspondence with the name of each element which includes a cell configuring the circuit to be analyzed, and the meaning or the relationship of...
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7131093 |
Methods and apparatus for creating a programmable link delay
In a first aspect, a first method of creating a programmable link delay during cycle simulation of a system is provided. The first method includes the steps of (1) modeling a system for cycle...
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7127385 |
Delay time estimation method and recording medium storing estimation program
The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which...
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7127686 |
Method for validating simulation results of a system as well as equivalence comparison of digital circuits based on said method
The invention creates a technology for validating simulation results. The quickly growing number of components in modern complex systems often necessitates the introduction of abstractions, that...
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7127693 |
Device for creating timing constraints
A datapath extraction unit extracts, from among datapaths on which a timing verification is to be performed, those datapaths from a netlist, timing constraints, and a cell library, that are...
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7127692 |
Timing abstraction and partitioning strategy
The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user...
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7127691 |
Method and apparatus for manufacturing test generation
An improved method and process is provided for verifying a digital logic design complies with certain manufacturing test rules or guidelines. A replacement is created for any portion of a design to...
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7124388 |
Methods to generate state space models by closed forms and transfer functions by recursive algorithms for RC interconnect and transmission line and their model reduction and simulations
There is provided a set of methods with the exact accuracy to effectively calculate the n-th order state space models of RC distributed interconnect and transmission line in closed forms in time...
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7120883 |
Register retiming technique
An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging...
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7120888 |
Method, system and storage medium for determining circuit placement
A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights...
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7117459 |
Layout check system
A layout check system checks whether a layout of a power source, a component including a power pin, and a bypass capacitor on a PCB and defined by layout data created using a CAD system allows the...
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7117466 |
System and method for correlated process pessimism removal for static timing analysis
A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in...
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7117457 |
Current scheduling system and method for optimizing multi-threshold CMOS designs
This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This...
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7117143 |
Clock distribution in a circuit emulator
Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including...
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7116746 |
Synchronous clock phase control circuit
A synchronous clock phase control circuit includes a T/8 step phase clock generation unit, a phase selection unit, and four synchronous clock generation units. The T/8 step phase clock generation...
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7117469 |
Method of optimizing placement and routing of edge logic in padring layout design
Methods for generating a padring layout design are described. These methods utilize automation while still allowing customization. Automation is emphasized as much as possible so that more time can...
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7117472 |
Placement of a clock signal supply network during design of integrated circuits
A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may...
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7114136 |
Method for VLSI system debug and timing analysis
A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a...
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7114139 |
Device and method for floorplanning semiconductor integrated circuit
A plurality of blocks are optimally placed within a short process time while minimizing the exceeding of the delay time. Input means receives information on a logic circuit having a hierarchical...
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7111260 |
System and method for incremental statistical timing analysis of digital circuits
The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes...
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7111259 |
Crosstalk mitigation method and system
A method and system of crosstalk mitigation in integrated circuits employs delay change curves (DCCs) and uses targeted transistor sizing and/or buffer insertion. Based on a timing graph, a longest...
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7111261 |
Method of determining library parameters using timing surface planarity
The present invention relates to a characterizing a timing delay curve of a circuit component, said timing delay curve having a first region and a second region. The method includes determining a...
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7111274 |
Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to...
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7109047 |
Method and device for analyzing circuits
A method of analyzing a circuit comprising a plurality of interconnects is disclosed herein. The method may comprise analyzing at least one electrical property associated with a first interconnect,...
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7107200 |
Method and apparatus for predicting clock skew for incomplete integrated circuit design
Prediction of a clock skew for an incomplete integrated circuit design, includes (a) selecting a first metal layer having at least one clock design figure, (b) placing, for a minimum clock skew...
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7107557 |
Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit
In a circuit simulation step, a cell transistor level net list is input, the slew of an input signal waveform and the magnitude of a load capacitance connected to a cell output terminal are varied...
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7107558 |
Method of finding critical nets in an integrated circuit design
A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an...
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7103855 |
Clock control circuit and method
A clock reproduction circuit for reproducing a data clock from a data signal is disclosed. The clock reproduction circuit includes a voltage controlled oscillator, a phase detector, a frequency...
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7103863 |
Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires,...
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7098696 |
Logic circuit and semiconductor integrated circuit
The invention provides a logic circuit to identify time difference between signals having a variation in delay, and an integrated circuit which can evaluate variations in delay among internal...
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7100125 |
Aggressor classification method for analyzing crosstalk of circuit
Functional and temporal aggressor classification methods that provide increased efficiency and accuracy for classifying aggressor signal lines of an integrated circuit for purposes of analyzing...
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7100132 |
Source synchronous timing extraction, cyclization and sampling
A translator tool for translating simulation test data generated to test clock recovery circuitry of a device from an event-based format to a cycle-based format readable by integrated circuit...
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7100136 |
LSI design system
Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart...
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7096433 |
Method for power consumption reduction
A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block...
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7096437 |
Method and apparatus for a chaotic computing module using threshold reference signal implementation
A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least...
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7096435 |
Method and apparatus for detecting the type of interface to which a peripheral device is connected
A peripheral device is connectable to a computer having one of a first interface and a second interface. The first interface communicates with the peripheral device over a differential data...
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7096443 |
Method for determining the critical path of an integrated circuit
A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical...
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7096442 |
Optimizing IC clock structures by minimizing clock uncertainty
Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a...
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7096438 |
Method of using clock cycle-time in determining loop schedules during circuit design
A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations; receiving a...
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7093211 |
Techniques for modeling current spreading uniformity in light emitting diodes
Techniques for automatically generating three dimensional geometric circuit models from a computer aided design (CAD) of a light emitting diode (LED) device. The models may comprise a robust...
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7093219 |
Techniques for using edge masks to perform timing analysis
Techniques are provided for more efficient timing analysis of user designs for programmable ICs. Initially, a graph is created that represents nodes and edges in a user design. Each edge in the...
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7093240 |
Efficient timing chart creation and manipulation
A program and method enables easy creation and manipulation of timing charts. The preferred embodiment employs off-the-shelf commercial software and uses Visual Basic commands to get timing chart...
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7093208 |
Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner...
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