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8178876 Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing  
A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test...
8176444 Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance  
A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to...
8161428 Method of predicting reliability of semiconductor device, reliability prediction system using the same and storage medium storing program causing computer to execute the same  
An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product. A method of predicting the reliability of a semiconductor device according to the...
8161425 Method and system for implementing timing aware metal fill  
An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to...
8156451 Method of manufacturing photomask  
A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level...
8156450 Method and system for mask optimization  
A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include...
8146024 Method and system for process optimization  
A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.
8146026 Simultaneous photolithographic mask and target optimization  
A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more...
8136056 Method and system for incorporation of patterns and design rule checking  
Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known g...
8136066 Apparatus and computer program product for semiconductor yield estimation  
A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The...
8132129 Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool  
A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a...
8122390 Charged particle beam writing apparatus, and apparatus and method for correcting dimension error of pattern  
A charged particle beam writing apparatus which the apparatus includes a first area density calculation unit and a first dimension error calculation unit. The apparatus includes a first dimension...
8122388 Phase-shifting masks with sub-wavelength diffractive optical elements  
The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a...
8122392 Robust design using manufacturability models  
The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity...
8117566 Method and system for representing manufacturing and lithography information for IC routing  
A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis,...
8112726 Phase-shifting masks with sub-wavelength diffractive optical elements  
The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a...
8108802 Method for forming arbitrary lithographic wavefronts using standard mask technology  
A desired set of diffracted waves using mask features whose transmissions are chosen from a set of supported values are generated. A representation of the mask as a set of polygonal elements is...
8108805 Simplified micro-bridging and roughness analysis  
The invention provides apparatus and methods for processing substrates using pooled statistically based variance data. The statistically based variance data can include Pooled Polymer De-protection...
8103986 Method and system for representing manufacturing and lithography information for IC routing  
A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis,...
8103981 Tool for modifying mask design layout  
An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of...
8102408 Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs  
Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs are provided. One method includes generating simulated...
8103982 System and method for statistical design rule checking  
Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules....
8095895 Method for defect diagnosis and management  
A method for defect diagnosis and management, which is implemented in a process for fabricating an article, comprising the following steps: obtaining an inspection image of the article, wherein the...
8091048 Method for predicting resist pattern shape, computer readable medium storing program for predicting resist pattern shape, and computer for predicting resist pattern shape  
The contour shape of an aerial image formed on a resist by projecting a test pattern onto the resist via a projection optical system is computed. The shape of a resist pattern formed by the...
8078998 Integrated circuits and methods of design and manufacture thereof  
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of...
8074188 Method for designing mask including forming a mesh dummy pattern  
A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern...
8056023 Determining manufacturability of lithographic mask by reducing target edge pairs used in determining a manufacturing penalty of the lithographic mask  
The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask...
8056029 Merging sub-resolution assist features of a photolithographic mask  
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second...
8051394 Yield evaluating apparatus and method thereof  
A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one...
8042070 Methods and system for analysis and management of parametric yield  
Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into...
8037430 Method for exploring feasibility of an electronic system design  
One inventive aspect relates to a method of determining an estimate of system-level yield loss for an electronic system comprising individual components subject to manufacturing process variability...
8028261 Method of predicting substrate current in high voltage device  
A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may...
8028254 Determining manufacturability of lithographic mask using continuous derivatives characterizing the manufacturability on a continuous scale  
The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic...
8015514 Random personalization of chips during fabrication  
Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The...
8010912 Method of shrinking semiconductor mask features for process improvement  
Provided is a method to design an integrated circuit. The method reduces a time delay between introduction of a new lithography process and a start of production. A first semiconductor mask is...
8010914 Circuit structure of integrated circuit  
A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second...
8010916 Test yield estimate for semiconductor products created from a library  
Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are...
8001495 System and method of predicting problematic areas for lithography in a circuit design  
A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict...
8001493 Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions  
An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the...
8001494 Table-based DFM for accurate post-layout analysis  
Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design...
7996795 Method and apparatus for performing stress modeling of integrated circuit material undergoing material conversion  
A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a...
7992108 Impurity concentration distribution predicting method and program for deciding impurity concentration distribution  
First and second evaluation substrates are prepared, a direction perpendicular to a surface of the first evaluation substrate being defined by first indices, and the direction defined by the first...
7984394 Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same  
A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring...
7937179 Dynamic inline yield analysis and prediction of a defect limited yield using inline inspection defects  
In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining...
7930656 System and method for making photomasks  
The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device...
7930655 Yield profile manipulator  
A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits...
7926004 Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects  
Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A...
7921387 Computational efficiency in photolithographic process simulation  
Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation...
7921391 Apparatus, method and computer-readable code for automated design of physical structures of integrated circuits  
Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is...
7913196 Method of verifying a layout pattern  
A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to...
Matches 1 - 50 out of 161 1 2 3 4 >