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7617474 |
System and method for providing defect printability analysis of photolithographic masks with job-based automation
Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A...
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7617469 |
Assertion description conversion device, method and computer program product
An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion...
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7617468 |
Method for automatic maximization of coverage in constrained stimulus driven simulation
A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit....
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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617466 |
Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device
A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths. The hazard check device includes a means for equivalent conversion...
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7617465 |
Method and mechanism for performing latch-up check on an IC design
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then...
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7617464 |
Verifying an IC layout in individual regions and combining results
When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter...
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7617463 |
Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit
In a power supply port decision step, first, a required minimum number of power supply ports for use in a test is found based on power consumption information and the required minimum number of...
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7614024 |
Method to implement metal fill during integrated circuit design and layout
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known...
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7614023 |
System for estimating a terminal capacitance and for characterizing a circuit
A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit includes providing first and second capacitance values associated with an upper and lower...
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7610571 |
Method and system for simulating state retention of an RTL design
Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL)...
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7610570 |
Method and mechanism for using systematic local search for SAT solving
An improved method and mechanism for designing and verifying an electrical circuit design is provided using an improved SAT-solver which uses complete assignments and systematic local search to...
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7610569 |
Chip design verification apparatus and data communication method for the same
A method of verifying a chip design includes: a software side operation step of transmitting output data generated by an operation of a software block to an interface unit, determining whether...
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7610568 |
Methods and apparatus for making placement sensitive logic modifications
Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already...
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7607116 |
Method and apparatus for verifying system-on-chip model
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification...
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7607115 |
System, method and computer program product for timing-independent sequential equivalence verification
A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to...
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7607114 |
Designer's intent tolerance bands for proximity correction and checking
A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into...
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7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry
Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first...
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7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method
An assertion generating system is disclosed. In an assertion generating system 207 , a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7600209 |
Generating constraint preserving testcases in the presence of dead-end constraints
Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is...
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7600208 |
Automatic placement of decoupling capacitors
Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In...
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7600206 |
Method of estimating the signal delay in a VLSI circuit
A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI...
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7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process
A technique for providing a product FIT rate is performed within electronic circuitry (e.g., one or more computerized devices). The technique involves receiving a Mean Time To Failure (MTTF) target...
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7596772 |
Methodology and system for setup/hold time characterization of analog IP
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The...
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7596771 |
Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same
The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element...
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7596770 |
Temporal decomposition for design and verification
Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations...
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7594209 |
Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis
A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is...
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7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been...
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7594207 |
Computationally efficient design rule checking for circuit interconnect routing design
Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements...
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7594202 |
Optimization of circuit designs using a continuous spectrum of library cells
The present invention comprises a method of optimizing a circuit design having a plurality of library cells. In one embodiment, the method includes the steps of providing a plurality of logically...
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7590968 |
Methods for risk-informed chip layout generation
A chip layout is generated based on a quantified fabrication process capability. A minimum required value is selected for a fabrication process capability factor associated with a fabrication...
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7590957 |
Method and apparatus for fixing best case hold time violations in an integrated circuit design
The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to...
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7590956 |
Methods of detecting unwanted logic in an operational circuit design
Methods of detecting unwanted logic in an integrated circuit (IC) design. Any unwanted logic added to a design (e.g., to monitor or interfere with operation of the design) will draw power from one...
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7590954 |
Test solution development method
A test solution for one or more circuits implementing a communication standard is based on a design specification received from a development organization and a communication standard. The test...
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7590953 |
Static timing analysis and dynamic simulation for custom and ASIC designs
A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the...
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7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets
The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing...
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7587693 |
Apparatus and method of delay calculation for structured ASIC
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a...
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7587692 |
Method and apparatus for full-chip thermal analysis of semiconductor chip designs
A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design...
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7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction
One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which...
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7587690 |
Method and system for global coverage analysis
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and...
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7587688 |
User-directed timing-driven synthesis
Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori...
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7586201 |
Wiring modeling technique
In a semiconductor device having wirings, a wiring modeling technique according to the present invention comprises the steps of selecting an arbitrary region of the semiconductor device;...
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7584460 |
Process and apparatus for abstracting IC design files
File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to...
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7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a...
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7584442 |
Method and apparatus for generating memory models and timing database
A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each...
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7584440 |
Method and system for tuning a circuit
The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit...
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7584439 |
Cell modeling for integrated circuit design with characterization of upstream driver strength
A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A...
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7584437 |
Assuring correct data entry to generate shells for a semiconductor platform
A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated...
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7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
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