Matches 351 - 400 out of 2111 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7444605 Generating a base curve database to reduce storage cost  
An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing...
7444274 Method and system for verifying circuit designs through propagation of assertions  
A method and system for verifying circuit designs through propagation of assertions within a circuit design. In an embodiment, a plurality of provided assertions a circuit design are propagated...
7444602 Method of generating ASIC design database  
When a function design has been carried out by an RTL description using an HDL language, a CPU of an integrated circuit design support apparatus writes data such as a simulation time, a layout...
7441210 On-the-fly RTL instructor for advanced DFT and design closure  
A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the...
7441214 Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media  
In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed...
7441212 State machine recognition and optimization  
State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each...
7441216 Applying CNF simplification techniques for SAT-based abstraction refinement  
The present embodiment keeps track of a set of resolution required for generating each one of the clauses added by the simplification method. This information is used by the method that generates...
7439637 Semiconductor circuit and resistance value controlling method  
A semiconductor circuit according to an embodiment of the invention includes: a terminal resistor circuit including a first Pch transistor; and a control circuit for outputting a control signal to...
7441215 Hierarchical netlist comparison by relevant circuit order  
The present invention uses the strength of modern hierarchical integrated circuit design to speed up the comparison of two netlists. Instead of working from bottom-up it can proceed with arbitrary...
7441213 Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof  
A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by...
7441211 Gate-length biasing for digital circuit optimization  
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a...
7437694 System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design  
A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is...
7437693 Method and system for s-parameter generation  
Disclosed are methods and systems for generating S-parameters. In some embodiments, the methods and systems comprise creating (e.g., extracting, calculating, generating), in part or whole into the...
7437696 Method and device for determining the time response of a digital circuit  
A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock...
7437689 Interconnect model-order reduction method  
An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is...
7437695 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices  
A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy...
7434181 Debugger of an electronic circuit manufactured based on a program in hardware description language  
A device for debugging an electronic circuit manufactured based on an initial program in hardware description language comprising an instrumentation unit capable of determining a first additional...
7434183 Method and system for validating a hierarchical simulation database  
System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing...
7434184 Method for detecting flaws in a functional verification plan  
This method uses 2 copies of the design under test. These 2 copies use different values (including primary inputs and initial states) to feed the supposedly irrelevant logic while using the same...
7434186 Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure  
Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C ∞ and inductances L ∞ of coplanar...
7434182 Method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip  
A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with...
7434185 Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data  
A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files...
7430728 Method and apparatus for selecting programmable interconnects to reduce clock skew  
A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock...
7428714 Line width error check  
A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line...
7428717 Integrated system noise management—system level  
An integrated software tool for system noise management is described. A system noise management suite for an assembly includes an integrated circuit design to be coupled to a circuit board design....
7428712 Design optimization using approximate reachability analysis  
Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using...
7426705 Combined hardware/software assertion checking  
Assertion checking is achieved by modifying a given set of assertions to include subsuming assertions that cover one or more of given assertions and also require less logic to implement, by...
7426704 Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling  
Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating...
7424417 System and method for clock domain grouping using data path relationships  
A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains...
7424693 Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins  
Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are...
7424145 Device and method for inspecting photomasks and products fabricated using the same  
An inspection device for photomasks and products fabricated using the same, capable of reducing the time from inspection to repair. A reference data generator generates reference data that is based...
7424418 Method for simulation with optimized kernels and debugging with unoptimized kernels  
A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the...
7424690 Interconnect integrity verification  
A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using...
7421669 Using constraints in design verification  
A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate...
7421675 Annotating timing information for a circuit design for increased timing accuracy  
A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and...
7421382 Data analysis techniques for dynamic power simulation of a CPU  
A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to...
7421671 Graph pruning scheme for sensitivity analysis with partitions  
A method of analyzing a circuit simulation comprising pruning a signal flow graph. Pruning the signal flow graph includes selecting a current vertex from a multiple input vertices in the signal...
7421668 Meaningful visualization of properties independent of a circuit design  
A property used in functional verification of a circuit design is debugged independently of the circuit design for which the property is intended. Visualization of the property under various...
7421672 Checks for signal lines  
Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline...
7421670 Chip development system enabled for the handling of multi-level circuit design data  
A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of...
7421673 Design checks for signal lines  
Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline...
7418680 Method and system to check correspondence between different representations of a circuit  
A method to check correspondence between different representations of a circuit may include abstracting a first computer language representation of the circuit to form a first abstract model of the...
7418688 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit  
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the...
7418683 Constraint assistant for circuit design  
A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types...
7418681 Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit  
A simulation system for verifying logic behavior of a semiconductor integrated circuit includes a reprogrammable semiconductor device having an interface circuit and a logic circuit; and an...
7418603 Mobile terminal, circuit board, circuit board design aiding apparatus and method, design aiding program, and storage medium having stored therein design aiding program  
The present invention provides a tamper resistant circuit board, an apparatus and method for aiding the design of the circuit board, a computer readable storage medium having stored therein a...
7418375 Load current evaluation device, load current evaluation method, and recording medium containing load current evaluation program  
A load electric current evaluating device includes a load electric current calculating section for calculating a load electric current flowing through a predetermined part of electric wiring...
7418684 Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks  
A method and an apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks have been disclosed. In one embodiment, the method includes determining a...
7418360 Project design method  
A configurable system for automating a control sequence, in particular a motion sequence, has several components which exchange in regular time intervals during the control sequence with each other...
7418682 Method and mechanism for performing DRC processing with reduced passes through an IC design  
A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is...
Matches 351 - 400 out of 2111 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >