|
Match
|
Document |
Document Title |
|
|
7469391 |
Method and device of analyzing crosstalk effects in an electronic device
For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model...
|
|
|
7467366 |
Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components
A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes...
|
|
|
7467363 |
Method for SRAM bitmap verification
A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method...
|
|
|
7467364 |
Database mining method and computer readable medium carrying instructions for coverage analysis of functional verification of integrated circuit designs
Database mining, analysis and optimization techniques in conjunction with the model-based functional coverage analysis are used to turn raw verification and coverage data into design intelligence...
|
|
|
7467365 |
Sanity checker for integrated circuits
This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method...
|
|
|
7464355 |
Timing analyzing method and apparatus for semiconductor integrated circuit
A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition. The best-case...
|
|
|
7464015 |
Method and apparatus for supporting verification, and computer product
In a verification supporting apparatus, when an obtaining unit obtains a verification scenario, a substituting unit substitutes an undefined value for a variable value in the verification scenario....
|
|
|
7464350 |
Method of and circuit for verifying a layout of an integrated circuit device
A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated...
|
|
|
7464351 |
Method enabling a standard CMOS fab to produce an IC to sense three-dimensional information using augmented rules creating mask patterns not otherwise expressible with existing fab rules
CMOS implementable three-dimensional silicon sensors are fabricated using a standard fab but using augmented rules that create mask patterns not expressible with existing fab rules. Standard fab...
|
|
|
7464349 |
Method and system or generating a current source model of a gate
Aspects for generating a current source model of a gate include extracting the current source model of the gate. The current source model of the gate is a function of time and output voltage of the...
|
|
|
7464348 |
Method and system for mapping source elements to destination elements as interconnect routing assignments
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for...
|
|
|
7464352 |
Methods for designing, evaluating and manufacturing semiconductor devices
A semiconductor device 100 has a configuration having a via 124 formed on a first interconnect 112 . A method for designing the semiconductor device 100 includes: calculating an anticipated...
|
|
|
7464354 |
Method and apparatus for performing temporal checking
An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During...
|
|
|
7461360 |
Validating very large network simulation results
A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws...
|
|
|
7460988 |
Test emulator, test module emulator, and record medium storing program therein
There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test...
|
|
|
7461359 |
Method and mechanism for determining shape connectivity
A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of...
|
|
|
7461364 |
Methods and readable media for using relative positioning in structures with dynamic ranges
Methods and readable media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed....
|
|
|
7458046 |
Estimating the difficulty level of a formal verification problem
Estimating the difficulty level of a verification problem includes receiving input comprising a design and properties that may be verified on the design. Verification processes are performed for...
|
|
|
7458048 |
Computer program product for verification of digital designs using case-splitting via constrained internal signals
A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design,...
|
|
|
7458045 |
Silicon tolerance specification using shapes as design intent markers
Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of...
|
|
|
7456660 |
Semiconductor device and display device
The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A...
|
|
|
7458060 |
Yield-limiting design-rules-compliant pattern library generation and layout inspection
A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that...
|
|
|
7458049 |
Aggregate sensitivity for statistical static timing analysis
A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution...
|
|
|
7458047 |
Method of designing layout of semiconductor integrated circuit and apparatus for doing the same
A method of designing a layout of a functional block and an on-chip capacitor in a semiconductor integrated circuit, includes the steps of (a) designing a layout of a capacitor/block including a...
|
|
|
7457728 |
Method and system for complex event processing
A method for complex event processing is disclosed. An event correlation engine detects various event correlation rules to analyze events to be detected and then retrieves event processing...
|
|
|
7458044 |
CDM ESD event simulation and remediation thereof in application circuits
Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit...
|
|
|
7454725 |
Apparatus and computer readable medium having program for analyzing distributed constant in a transmission line
The invention is aimed to analyze the characteristics of a transmission line only by inputting the specific distributed parameters without mesh dividing the transmission line to be analyzed into...
|
|
|
7454324 |
Selection of initial states for formal verification
A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification...
|
|
|
7454721 |
Method, apparatus and computer program product for optimizing an integrated circuit layout
A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact...
|
|
|
7454723 |
Validation of electrical performance of an electronic package prior to fabrication
An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a...
|
|
|
7454727 |
Method and Apparatus for Solving Sequential Constraints
Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior....
|
|
|
7454726 |
Technique for generating input stimulus to cover properties not covered in random simulation
A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where...
|
|
|
7454719 |
System and method for calculating effective capacitance for timing analysis
A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an...
|
|
|
7454323 |
Method for creation of secure simulation models
Method and apparatus for security systems are provided to protect electronic designs from unauthorized usage. An obfuscation system is provided for creating secure simulation models of IP cores...
|
|
|
7454724 |
Method and apparatus distribution power suply pad of semiconductor integrated circuit
A method for accurately determining the provisional quantity and provisional locations of power supply pads prior to detailed layout of a semiconductor integrated circuit. The method decreases...
|
|
|
7454731 |
Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques
Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a...
|
|
|
7451417 |
Timing annotation accuracy through the use of static timing analysis tools
A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional...
|
|
|
7451411 |
Integrated circuit design system
The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein...
|
|
|
7451414 |
Method for determining relevant circuit parts in a circuit in the event of loading with a temporally variable signal
Method for determining relevant circuit parts in a circuit in the event of loading with a temporally variable signal comprises providing a computer-implemented model of the circuit, in which the...
|
|
|
7451375 |
Directed falsification of a circuit
In one embodiment, a method for directed falsification of a circuit includes selecting a partition of a state space of the circuit. The partition includes only a portion of the state space and is...
|
|
|
7451412 |
Speeding up timing analysis by reusing delays computed for isomorphic subcircuits
One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block...
|
|
|
7451415 |
Method for predicting inductance and self-resonant frequency of a spiral inductor
In this invention, a closed-form integral model for on-chip suspended rectangular spiral inductor is presented. The model of this invention bases on the Kramers-Kronig relations, field theory, and...
|
|
|
7451413 |
Methods of minimizing leakage current by analyzing post layout information and associated threshold voltage and leakage current
Methods, systems and computer program products for automatically minimizing leakage current in a circuit design can include post layout delay information of a circuit that meets timing limits is...
|
|
|
7448004 |
Method and management tool for assessing an electronic design validation process
A method, management tool, or spreadsheet device that allows a user to analyze, compare, and assess various aspects of an electronic design validation process for an integrated circuit. The...
|
|
|
7448010 |
Methods and mechanisms for implementing virtual metal fill
A method for implementing virtual metal fill includes inserting metal fill data into a layout record based on one or more rules, extracting capacitance from the layout record to create a...
|
|
|
7448003 |
Signal flow driven circuit analysis and partitioning technique
A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital...
|
|
|
7447619 |
Apparatus and method for composite behavioral modeling for multiple-sourced integrated circuits
An apparatus and method for simulation and testing of electronic systems using a single model that has the composite behavioral information of multiple parts. The single model allows the designer...
|
|
|
7448005 |
Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver
A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial...
|
|
|
7447966 |
Hardware verification scripting
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification...
|
|
|
7448006 |
Logic-synthesis method and logic synthesizer
The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes...
|