Matches 251 - 300 out of 2116 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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7493577 Automatic recognition of geometric points in a target IC design for OPC mask quality calculation  
A method and system is provided for automatically recognizing geometric points of features in a target design for OPC mask quality calculation. For each feature in the target design, x, y points...
7490306 Sub-system power noise suppression design procedure  
Aspects of the disclosure provide methods and systems to design a distributed discrete capacitor bank incorporating power plane capacitance to concentrate the suppression of AC coupling to the...
7490305 Method for driving values to DC adjusted/untimed nets to identify timing problems  
A method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized,...
7488691 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device of the present invention includes a step (S 100 ) of judging whether an interconnect pitch of an interconnect pattern having the smallest interconnect...
7490304 Determining geometrical configuration of interconnect structure  
Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method...
7490307 Automatic generating of timing constraints for the validation/signoff of test structures  
An apparatus comprising a database, an input module and a software tool. The database may be configured to generate one or more database files representing a design of an integrated circuit (IC)....
7487571 Control adjustable device configurations to induce parameter variations to control parameter skews  
A method is used for configuring an electronic device to reduce a skew of a parameter. The method includes a step of incorporating a plurality of controllable built-in parameter variation adjusting...
7489139 System and method for checking decoupling of power supply in printed wiring board  
A checking unit includes a power net extractor for extracting a power net with power attribution, which is segmented by a power-decoupling element, with reference to circuit design data of a...
7487480 Method for estimating aggregate leakage of transistors  
A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for...
7487474 Designing an integrated circuit to improve yield using a variant design element  
An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A...
7487483 Clock model for formal verification of a digital circuit description  
The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the...
7487476 Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool  
A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a...
7487486 Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations  
The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization ( 1 ). Significant research has been...
7487479 Systematic approach for applying recommended rules on a circuit layout  
A method and apparatus for enforcing design for manufacturability rules on a circuit layout is provided. A tool receives a first set of design rules, to be applied to the circuit layout, which must...
7487475 Systems, methods, and apparatus to perform statistical static timing analysis  
A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit...
7487487 Design structure for monitoring cross chip delay variation on a semiconductor device  
The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization ( 1 ). Significant research has been...
7487478 Method for dynamically adjusting parameter values of part heights to verify distances between parts  
A method for dynamically adjusting parameter values of part heights to verify the distances between parts is provided. The method comprises, inputting multiple sets of limiting conditions for part...
7484187 Clock-gating through data independent logic  
Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data...
7484194 Automation method and system for assessing timing based on Gaussian slack  
An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times...
7483823 Building integrated circuits using logical units  
Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models,...
7484192 Method for modeling metastability decay through latches in an integrated circuit model  
Mechanisms for modeling metastability decay through latches in an integrated circuit model are provided. Asynchronous clock boundaries are identified in the integrated circuit model and latches in...
7484188 On-chip test circuit and method for testing of system-on-chip (SOC) integrated circuits  
A system and method of testing IP cores contained in a system-on-chip integrated circuit is disclosed. An operation command is received on an input/output port of the circuit. The operation command...
7480607 Circuit design verification  
A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically...
7480879 Substrate noise tool  
System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse...
7480610 Software state replay  
A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for...
7480878 Method and system for layout versus schematic validation of integrated circuit designs  
A method and system for validating selected layers of an integrated circuit design. A rundeck is edited to include IC layers and device structures of interest that may require validation. In some...
7480886 VLSI timing optimization with interleaved buffer insertion and wire sizing stages  
The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads....
7480875 Method of designing a semiconductor integrated circuit  
In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while...
7480874 Reliability analysis of integrated circuits  
Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance...
7480608 Method and system for reducing storage requirements of simulation data via KEYWORD restrictions  
Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list...
7478348 Method and apparatus of rapid determination of problematic areas in VLSI layout by oriented sliver sampling  
A method and system for identifying problematic areas in a very large scale integrated (VLSI) layout. The method and system includes defining one or more sample area and overlaying the one or more...
7478349 Automatically synchronizing timed circuits on I/O Devices  
System and method for automatically synchronizing multiple I/O devices with homogeneous and/or heterogeneous timing and I/O channel types. A graphical program specifying configuration and operation...
7478029 Cable simulation device and method  
A cable simulator that comprises an input device configured to receive a communication signal. The cable simulator further comprises a circuit configured to simulate attenuation in both the...
7478346 Debugging system for gate level IC designs  
A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump...
7478347 Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus  
A semiconductor manufacturing apparatus having a plurality of portions according to this invention includes a storage device which stores, for each portion, information representing the lapsed time...
7475367 Memory power models related to access information and methods thereof  
A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating...
7475370 System for verification using reachability overapproximation  
A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design,...
7475368 Deflection analysis system and method for circuit design  
A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material...
7475369 Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification  
Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the...
7474011 Method for improved single event latch up resistance in an integrated circuit  
A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest...
7472363 Semiconductor chip design having thermal awareness across multiple sub-system domains  
A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the...
7472364 Method of matching layout shapes patterns in an integrated circuit using walsh patterns  
A method for matching patterns, based on an orthogonal sub-space projection of layout shapes using Walsh patterns, performs a preliminary density feature extraction of a circuit design layout,...
7472055 Method and system for deterministic control of an emulation  
An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with...
7472370 Comparing graphical and netlist connections of a programmable logic device  
A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD...
7472361 System and method for generating a plurality of models at different levels of abstraction from a single master model  
A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that...
7469392 Abstraction refinement using controllability and cooperativeness analysis  
One embodiment of the present invention provides a system that refines an abstract model. Note that abstraction refinement is commonly used in formal property verification. During operation, the...
7469394 Timing variation aware compilation  
Design compilation software uses statistical analysis techniques to account for variations in device attributes. A compilation phase determines statistical attributes of edges and other elements of...
7469399 Semi-flattened pin optimization process for hierarchical physical designs  
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of...
7469393 Method and device for supporting verification, and computer product  
In a verification support device, a logical expression expressing an operation of a pattern generator can be acquired. The pattern generator includes a basic pattern generator, priority pattern...
7469398 IP placement validation  
A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information...
Matches 251 - 300 out of 2116 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >