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7543260 |
Design supporting system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, and computer readable medium for supporting design of semiconductor integrated circuit
A design supporting system of a semiconductor integrated circuit includes a unit that converts a defective circuit pattern into computer detectable information when a layout of the chip is...
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7543259 |
Method and device for deciding support portion position in a backup device
A host computer 80 for wholly controlling an electronic component mounting line displays a surface side image and a reverse side image which respectively show a surface side and a reverse side of...
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7543256 |
System and method for designing an integrated circuit device
A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is...
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7543257 |
Apparatus for giving assistance in analyzing deficiency in RTL-input program and method of doing the same
An apparatus for giving assistance in analyzing deficiency in a RTL-input program, includes a partial RTL creator which creates partial RTL description data containing logic description identical...
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7543258 |
Clock design apparatus and clock design method
A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust...
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7539954 |
OPC simulation model using SOCS decomposition of edge fragments
A system for estimating image intensity within a window area of a wafer using a SOCS decomposition to determine the horizontal and vertical edge fragments that correspond to objects within the...
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7539957 |
Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks
Methods and apparatus for testing integrated circuits are provided. Integrated circuits sometimes contain repeating blocks of identical circuitry. Each identical circuit block contains scan chain...
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7539958 |
Estimation of average-case activity for digital circuits
The present invention provides a method for estimating the average-case activity in a digital circuit. The method includes the steps of assigning initial activity values to outputs of flops in the...
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7539961 |
Library-based solver for modeling an integrated circuit
A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for...
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7536662 |
Method for recognizing and verifying FIFO structures in integrated circuit designs
First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural...
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7536288 |
Method, system and program product supporting user tracing in a simulator
According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more...
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7536667 |
Method of semiconductor device and design supporting system of semiconductor device
A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval...
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7536670 |
Method for verifying and choosing lithography model
A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration...
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7536663 |
Method and apparatus for quantifying the timing error induced by an impedance variation of a signal path
In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the...
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7533357 |
Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis
A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution...
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7533359 |
Method and system for chip design using physically appropriate component models and extraction
An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into...
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7530036 |
Random test generation using an optimization solver
An optimization process is repeatedly invoked over an input, which includes the set of constraints and the objective function. The input of each invocation is randomly modified, so as to cause the...
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7530048 |
Defect filtering optical lithography verification process
An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at least one design phase or...
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7530037 |
Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods
A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor...
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7526747 |
Inspection method and inspection system using charged particle beam
Secondary electrons and back scattered electrons generated by irradiating a wafer to be inspected such as a semiconductor wafer with a charged particle beam are detected by a detector. A signal...
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7526740 |
System and method for automated electronic device design
A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher...
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7526419 |
Methods for reconstructing data from simulation models
Methods for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a...
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7526748 |
Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium
A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first...
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7526742 |
One-pass method for implementing a flexible testbench
A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first...
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7526749 |
Methods and apparatus for designing and using micro-targets in overlay metrology
Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first...
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7526741 |
Microfluidic design automation method and system
The present invention generally relates to microfluidics and more particularly to the design of customized microfluidic systems using a microfluidic computer aided design system. In one embodiment...
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7523425 |
Test case generation algorithm for a model checker
A method for testing hardware and software system design. An abstract system description is used to design hardware/software systems and generated test cases are reused to verify the correctness of...
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7523424 |
Method and system for representing analog connectivity in hardware description language designs
System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have...
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7523029 |
Logic verification and logic cone extraction technique
Logic verification is performed based on correspondence information and compile information. The correspondence information specifies information on pairs of fragments of descriptions to be...
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7523427 |
Timing analyzer apparatus and timing analysis program recording medium
By multiplying a square root of a sum of squares of a standard deviation of cells constituting a target circuit by a weight, or by calculating a square root of a sum of squares of a weighted...
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7523030 |
Simulation system and computer program
Disclosed is a simulation system for displaying source lines in a behavior level description during execution of simulation to indicate the execution status of a conditional branch statement in a...
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7519936 |
Unallocatable space depicting system and method for a component on a printed circuit board
An unallocatable space depicting system is provided for depicting an unallocatable space for a component. The component forms a component shape on a printed circuit board layout. The unallocatable...
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7519930 |
Method of calculating a model formula for circuit simulation
A circuit simulator for a semiconductor device with reduced channel length includes a method of calculating a model formula for circuit simulation of a semiconductor device; calculating first...
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7519941 |
Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry
Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and...
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7519939 |
Method and program for supporting register-transfer-level design of semiconductor integrated circuit
A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a...
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7519932 |
System and method for analyzing crosstalk occurring in a semiconductor integrated circuit
A system for analyzing crosstalk occurring in a semiconductor integrated circuit, includes calculating timing windows of first and second wires under a first and second analysis conditions, a...
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7519928 |
Method for propagating phase constants in static model analysis of circuits
A method for propagating phase constants for static circuit model analysis is provided. The mechanisms of the illustrative embodiments make use of multiple phases of constant propagation to handle...
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7519925 |
Integrated circuit with dynamically controlled voltage supply
An electronic system ( 10 ). The system comprises circuitry (P 1 ) for receiving a system voltage from a voltage supply. The system also comprises circuitry ( 14 1 ), responsive to the system...
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7519929 |
Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules
In some embodiments, a method is provided for determining a localized region of overlap of first and second features from respective first and second conductive layers, and determining which...
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7516428 |
Microwave circuit performance optimization by on-chip digital distribution of operating set-point
A method and circuit are outlined allowing the performance of an RF circuit to be established through the use of digital calibration data, which is stored within a programmable memory store and...
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7516430 |
Generating testcases based on numbers of testcases previously generated
A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or...
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7516431 |
Methods and apparatus for validating design changes without propagating the changes throughout the design
Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design....
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7516427 |
Input capacitance characterization method in IP library
A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP...
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7512908 |
Method and apparatus for improving SRAM cell stability by using boosted word lines
The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage...
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7512915 |
Embedded test circuit for testing integrated circuits at the die level
A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing...
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7512912 |
Method and apparatus for solving constraints for word-level networks
The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is...
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7512918 |
Multimode delay analysis for simplifying integrated circuit design timing models
A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc...
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7512925 |
System and method for reducing test time for loading and executing an architecture verification program for a SoC
A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments...
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7512911 |
Method for creating a parameterized cell library dual-layered rule system for rapid technology migration
A parameterized cell library including variable names corresponding to characteristics of components on an integrated circuit design may reference variable values stored in a first rule layer via...
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7512917 |
Method for verifying safety apparatus and safety apparatus verified by the same
A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of...
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