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7275226 |
Method of performing latch up check on an integrated circuit design
A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within...
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7275231 |
High level validation of designs and products
A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a...
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7275227 |
Method of checking optical proximity correction data
A method of inspecting full-chip mask data to locate layout pattern design induced defects and weak points that cause functional failure or performance degradation for integrated circuits (ICs)...
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7272806 |
System and method for evaluating power and ground vias in a package design
A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of...
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7272810 |
Semiconductor integrated circuit having multi-level interconnection, CAD method and CAD tool for designing the semiconductor integrated circuit
A computer-aided design method of an integrated circuit includes: calculating current dissipation consumed by logic elements, in a ladder network embracing a plurality of current paths connected...
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7272805 |
System and method for converting a flat netlist into a hierarchical netlist
System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and...
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7269810 |
Global equivalent circuit modeling system for substrate mounted circuit components incorporating substrate dependent characteristics
The present invention is a substrate dependent circuit modeling system for substrate-mounted components. The height and dielectric constant of a substrate have a significant impact on the frequency...
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7269809 |
Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits
Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate...
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7269804 |
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution...
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7269808 |
Design verification
A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically...
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7269807 |
Area ratio/occupancy ratio verification method and pattern generation method
Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed...
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7266792 |
Automated noise convergence for cell-based integrated circuit design
According to some embodiments, a noise problem is automatically analyzed within the context of a cell-based integrated circuit design to identify an adjustment to the design in view of the...
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7266488 |
Programmable pattern generation for dynamic bus signal integrity analysis
A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus...
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7266795 |
System and method for engine-controlled case splitting within multiple-engine based verification framework
A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of...
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7266794 |
Apparatus for and method of analyzing transmission characteristics of a circuit apparatus
A method of analyzing transmission characteristics of signal wiring in a circuit apparatus including the signal wiring and insulative layer is disclosed. The transmission characteristics are...
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7266791 |
High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium
A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality...
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7263672 |
Methods, systems, and data models for describing an electrical device
A method and system are described for creating a metadata text file corresponding to a geometry of a physical layout and/or a circuit layout of an electrical device. The layouts are defined in a...
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7263478 |
System and method for design verification
An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility...
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7263676 |
Method and apparatus for detecting and analyzing the propagation of noise through an integrated circuit
One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a...
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7260801 |
Delay computation speed up and incrementality
A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output...
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7260799 |
Exploiting suspected redundancy for enhanced design verification
A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the...
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7260797 |
Method and apparatus for estimating parasitic capacitance
One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the...
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7260796 |
Capacitance measurements for an integrated circuit
A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to...
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7260798 |
Compilation of remote procedure calls between a timed HDL model on a reconfigurable hardware platform and an untimed model on a sequential computing platform
A system is described for managing interaction between an untimed HAL portion and a timed HDL portion of the testbench, wherein the timed portion is embodied on an emulator and the un-timed portion...
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7260794 |
Logic multiprocessor for FPGA implementation
A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein...
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7260803 |
Incremental dummy metal insertions
A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool....
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7260800 |
Method and apparatus for initial state extraction
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM DFG and HLM DFG . RTLM DFG and HLM DFG are then put into...
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7257787 |
Method for reducing an equivalent resistance in an IC layout
A method of the invention is used for checking the via density between two adjacent layers of an IC layout. The method includes selecting a first metal layer and a second metal layer, wherein the...
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7257786 |
Method and apparatus for solving constraints
An approach to solving combinational constraints, comprising compile and generate phases, is presented. The compile phase constructs successive sets of constraints, each with a solution generator,...
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7257784 |
Method for integrally checking chip and package substrate layouts for errors
A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first...
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7257789 |
LSI design method
An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective...
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7254804 |
Method of verifying corrected photomask-pattern results and device for the same
A method of verifying photomask-pattern-correction results includes steps of cutting away photomask patterns of a region to be subjected to correction, forming photoresist models used for execution...
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7254803 |
Test structures for feature fidelity improvement
Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base...
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7254790 |
Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops
A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into...
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7254791 |
Method of measuring test coverage of backend verification runsets and automatically identifying ways to improve the test suite
The quality assurance of all released runset files should ideally be 100% complete to ensure the best quality of the runsets. This means that the designs used for testing should be sufficient to...
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7254792 |
Accounting for the effects of dummy metal patterns in integrated circuits
In one embodiment, a level in a process technology for an integrated circuit that has dummy metal patterns is represented as a level in a process model. The level of the process model may comprise...
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7254793 |
Latch modeling technique for formal verification
A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized...
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7251792 |
Net list creating method, net list creating device, and computer program thereof
It is intended to provide net list creating method, net list creating device, and computer program thereof capable of creating net list of memory space by selecting optimum combination of memory...
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7251794 |
Simulation testing of digital logic circuit designs
A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more...
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7251796 |
Predictive event scheduling in an iterative tran resolution network
A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a...
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7249333 |
Quantified boolean formula (QBF) solver
Quantified Boolean formula (QBF) techniques are used in determining QBF satisfiability. A QBF is broken into component parts that are analyzable by a satisfiability (SAT) solver. Each component is...
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7249331 |
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
A method for estimating power dissipated by processor core processing a workload includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual...
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7249332 |
Using local reduction in model checking to identify faults in logically correct circuits
A method and computer program for verifying a design of a circuit comprises selecting a portion of a model of the design having a plurality of inputs and outputs; providing a property for the...
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7246335 |
Analyzing substrate noise
In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm...
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7246334 |
Topological analysis based method for identifying state nodes in a sequential digital circuit at the transistor level
State nodes in a sequential digital circuit are identified using a graph-based method based upon the topology of the circuit. In accordance with the method, the device level circuit netlist is...
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7246056 |
Runtime parameter mapping for system simulation
An electronic device and method are provided to enable simulation of a system while minimizing a requirement to reanalyze or recompile topology information during subsequent simulations of the...
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7246332 |
Methods, systems and media for functional simulation of noise and distortion on an I/O bus
Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments...
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7243317 |
Parameter checking method for on-chip ESD protection circuit physical design layout verification
A checking mechanism for complete full-chip ESD protection circuit design and layout verification at layout level identifies all of both intentional and parasitic ESD devices contained in the...
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7243320 |
Stochastic analysis process optimization for integrated circuit design and manufacture
An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices,...
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7243323 |
Integrated circuit chip design
Method of developing a model of a circuit design including the steps of generating four different path-tracing runs, creating four arcs from the four different path-tracing runs, and combining the...
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