|
Match
|
Document |
Document Title |
|
|
7315995 |
Semiconductor integrated circuit designing method and program
An object of the present invention is to prevent occurrence of an unconnected terminal during arrangement and connection, shorten the time required for automatic arrangement and connection, improve...
|
|
|
7315996 |
Method and system for performing heuristic constraint simplification
A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the...
|
|
|
7315994 |
Method and device for automated layer generation for double-gate FinFET designs
In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each...
|
|
|
7315992 |
Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated...
|
|
|
7313773 |
Method and device for simulator generation based on semantic to behavioral translation
Generating a simulator from an architecture description. A target architecture model described in an architecture description language (ADL) is accessed. The model comprises a semantic...
|
|
|
7313774 |
Method and apparatus for associating an error in a layout with a cell
One embodiment of the present invention provides a system that associates an error in a layout with a cell. During operation, the system receives a layout which is designed to create a target...
|
|
|
7313772 |
Systems, methods, and media for block-based assertion generation, qualification and analysis
Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The...
|
|
|
7313770 |
MOSFET modeling for IC design accurate for high frequencies
The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a...
|
|
|
7310792 |
Method and system for modeling variation of circuit parameters in delay calculation for timing analysis
A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in...
|
|
|
7310791 |
Method for correcting layout errors
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least...
|
|
|
7310790 |
Automatic symbolic indexing methods for formal verification on a symbolic lattice domain
Processes for formal verification of circuits and other finite-state systems are disclosed. For one embodiment, a process is disclosed to provide for significantly reduced computation through...
|
|
|
7308658 |
Method and apparatus for measuring test coverage
A method, computer program product, and data processing system for determining test sequences' coverage of events in testing a semiconductor design are disclosed. Test patterns are randomly...
|
|
|
7308659 |
Apparatus and method for RTL modeling of a register
The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are...
|
|
|
7308665 |
Method and apparatus for analyzing clock-delay, and computer product
An input unit receives circuit information on a circuit. A first calculating unit calculates delay-distribution information of a data path and delay-distribution information of a clock path, based...
|
|
|
7308663 |
Circuit design verification using checkpointing
A design verification method, comprising providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, M checkpointed...
|
|
|
7308662 |
Capacitance modeling
A method of modeling capacitance for all practical 2D on-chip wire structures including coplanar and microstrip structures. The method includes using a field lines approach ( 600 ) to obtain...
|
|
|
7308660 |
Calculation system of fault coverage and calculation method of the same
A calculation system of fault coverage includes a data acquiring module acquiring layout information and gate net data, a layout analysis and fault link module extracting a layout element...
|
|
|
7308661 |
Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications
A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and...
|
|
|
7305636 |
Method and system for formal unidirectional bus verification using synthesizing constrained drivers
A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level...
|
|
|
7305642 |
Method of tiling analog circuits
The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic...
|
|
|
7305639 |
Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip
A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and...
|
|
|
7305634 |
Method to selectively identify at risk die based on location within the reticle
A method and system of selectively identifying at risk die based on location within the reticle. Reticle and stepping information is stored in a database. All reticle shots in a wafer and in a lot...
|
|
|
7302654 |
Method of automating place and route corrections for an integrated circuit design from physical design validation
A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit...
|
|
|
7302656 |
Method and system for performing functional verification of logic circuits
A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by...
|
|
|
7302655 |
Method for verifying a circuit design by assigning numerical values to inputs of the circuit design
A method for verifying a circuit design includes a step of assigning numerical values 1/a i to input ports of the circuit design according to a function a i+1 =(a i −1) 2 +1, wherein i...
|
|
|
7302658 |
Methods for evaluating quality of test sequences for delay faults and related technology
In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so...
|
|
|
7302651 |
Technology migration for integrated circuits with radical design restrictions
A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are...
|
|
|
7302664 |
System and method for automatic insertion of on-chip decoupling capacitors
A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise...
|
|
|
7299429 |
System and method for providing burst licensing in a circuit simulation environment
A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the...
|
|
|
7299436 |
System and method for accurately modeling an asynchronous interface using expanded logic elements
A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to...
|
|
|
7299428 |
Model stamping matrix check technique in circuit simulator
The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining...
|
|
|
7299435 |
Frequency dependent timing margin
A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the...
|
|
|
7299445 |
Nonlinear receiver model for gate-level delay calculation
A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions)....
|
|
|
7299434 |
Slack value setting method, slack value setting device, and recording medium recording a computer-readable slack value setting program
A slack value setting device comprises a worst path selecting section, a first slack value calculating section for calculating slack value set up to each of the transit pins on the worst path, a...
|
|
|
7296252 |
Clustering techniques for faster and better placement of VLSI circuits
A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given...
|
|
|
7296250 |
Method and system for characterizing electronic circuitry
According to the invention a characteristic property of an electronic circuit component depending on at least one variable (X 1 , X 2 ) is approximated by an approximating function. This is...
|
|
|
7293248 |
System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis
There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least...
|
|
|
7293247 |
Encapsulating parameterized cells (pcells)
A method for encoding elements of an electronic design generates a flattened hierarchy of a parameterized cell of the electronic design, selects common and unique parameters of each element in the...
|
|
|
7290235 |
Method and system for embedding wire model objects in a circuit schematic design
The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing...
|
|
|
7290230 |
System and method for verifying a digital design using dynamic abstraction
A method for verifying a digital system design is provided. A first abstraction of a digital system design is performed to obtain an abstract model of the digital system design. One or more first...
|
|
|
7290229 |
Method and system for optimized handling of constraints during symbolic simulation
A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing...
|
|
|
7287236 |
Electronic device connectivity analysis methods and systems
Techniques for determining and verifying connectivity in an electronic device from a representation of the electronic device are disclosed. Connectivity is determined by identifying electronic...
|
|
|
7287235 |
Method of simplifying a circuit for equivalence checking
A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a...
|
|
|
7287238 |
Method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation
The present invention is directed to a method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation. Addresses may be provided to...
|
|
|
7284214 |
In-line XOR checking of master cells during integrated circuit design rule checking
Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then...
|
|
|
7284210 |
Method for reconfiguration of random biases in a synthesized design without recompilation
A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver...
|
|
|
7284212 |
Minimizing computational complexity in cell-level noise characterization
Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and...
|
|
|
7284215 |
Method to solve similar timing paths
A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the...
|
|
|
7284217 |
Method of LSI designing and a computer program for designing LSIS
An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a...
|
|
|
7283942 |
High speed techniques for simulating circuits
The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called...
|