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7340702 |
Method and apparatus for induction proof
Inductive proof can be an improvement to bounded verification. Forward and backward inductive proof methods are disclosed, which can improve the process of verifying properties of circuit designs....
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7340703 |
Test structures and method for interconnect impedance property extraction
A method and test structures are disclosed for characterizing interconnects of an integrated circuit. The method provides a set of test structures and determines a unit impedance property of each...
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7340707 |
Automatic tuning of signal timing
A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various...
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7340701 |
Layout verification method and device
There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring...
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7340706 |
Method and system for analyzing the quality of an OPC mask
The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the...
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7340705 |
In-circuit device, system and method to parallelize design and verification of application-specific integrated circuits (“ASICs”) having embedded specialized function circuits
An in-circuit design and verification device, system and method are disclosed for cooperatively designing and verifying application-specific integrated circuit device prior to fabrication by...
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7340696 |
Automated design process and chip description system
An automated design process and chip description system is disclosed. The automated design process and chip description system compensates for the loss in design information that occurs when the...
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7340698 |
Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components
A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating...
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7340697 |
Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies
Methods and apparatus are described that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single master design environment. The master...
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7340692 |
System LSI development apparatus and the method thereof for developing a system optimal to an application
In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor...
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7340386 |
Method and system for quantifying the quality of diagnostic software
A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a...
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7340712 |
System and method for creating a standard cell library for reduced leakage and improved performance
The present invention provides a system and method for providing a standard cell library for reduced leakage and improved performance. The standard cell library comprises at least two sets of...
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7340710 |
Integrated circuit binning and layout design system
A method for binning and layout of an integrated circuit design which includes providing a table setting forth predefined widths of signal wires and corresponding spacing to shield wires,...
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7337418 |
Structural regularity extraction and floorplanning in datapath circuits using vectors
In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The...
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7337100 |
Physical resynthesis of a logic design
A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed,...
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7337426 |
Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein
There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a...
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7337419 |
Crosstalk noise reduction circuit and method
In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that...
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7337414 |
Logical equivalence verifying device, method, and computer-readable medium thereof
The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device...
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7337416 |
Method of using strongly coupled components to estimate integrated circuit performance
A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When estimating...
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7332380 |
Pattern design method and program of a semiconductor device including dummy patterns
According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a...
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7333926 |
Method, apparatus, and computer program product for facilitating modeling of a combinatorial logic glitch at an asynchronous clock domain crossing
A method, apparatus and computer program product are provided for facilitating combinatorial logic modeling at an asynchronous clock domain crossing. The modeling technique employs a simulation...
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7334201 |
Method and apparatus to measure hardware cost of adding complex instruction extensions to a processor
An apparatus, method, and computer-readable media that provide fast and accurate prediction of the hardware cost of logic to extend a processor. Aspects of the invention enable designers to explore...
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7331028 |
Engineering change order scenario manager
A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by...
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7331029 |
Method and system for enhancing circuit design process
A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the...
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7331024 |
Power-consumption calculation method and apparatus
An apparatus for calculating power consumption includes a behavioral synthesis unit for generating a clock-level description by behavioral synthesis of an algorithm description; a clock-level...
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7331022 |
Method and apparatus for automating pin assignments
A method for automating pin assignments through an electronic design automation (EDA) development tool is provided. In the method, components for a chip design are selected and a board in which the...
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7328423 |
Method for evaluating logic functions by logic circuits having optimized number of and/or switches
A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency...
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7328414 |
Method and system for creating and programming an adaptive computing engine
A system for creating an adaptive computing engine (ACE) includes algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations, and provides mapping of the...
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7328143 |
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened...
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7325218 |
Wiring method, program, and apparatus
A problem is efficiently solved by giving a proper adjacent spacing condition only to nets having such a problem that a wiring delay and crosstalks are caused. A wiring processing unit executes a...
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7325208 |
Method, apparatus and system for inductance modeling in an electrical configuration
Embodiments of the present invention provide a method, apparatus and system for inductance modeling. According to some exemplary embodiments, a method for inductance modeling may include...
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7325211 |
Clock skew modelling using delay stamping
A method for determining clock skew to avoid hold time violations is provided. The method includes obtaining a total delay to a source by adding a first delay associated with each of the delay...
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7325209 |
Using patterns for high-level modeling and specification of properties for hardware systems
This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language...
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7322018 |
Method and apparatus for computing feature density of a chip layout
One embodiment of the present invention provides a system that computes feature density for a number of areas within a layout by moving a window across the layout, which allows the system to...
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7322016 |
Impact checking technique
A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is in...
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7322017 |
Method for verification using reachability overapproximation
A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design,...
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7320090 |
Methods, systems, and media for generating a regression suite database
Methods, systems and media for generating an improved regression suite by applying harvesting models and/or regression algorithms to tests utilized in verification of a system are disclosed. In one...
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7320116 |
Method of generating cell library data for large scale integrated circuits
A method of generating library data for a cell constructed of interconnected MOS transistors, includes a resistance extraction step which extracts source and drain resistances according to source...
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7320114 |
Method and system for verification of soft error handling with application to CMT processors
A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is...
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7318207 |
Apparatus and method for verifying layout interconnections using power network analysis
A method for verifying layout interconnections includes extracting a loop circuit as a loop portion in a first circuit model. The first circuit model includes first branch interconnections included...
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7318204 |
Synthesizing semiconductor process flow models
Systems and methods of modeling a best-guess semiconductor process flow for fabricating a desired semiconductor device are provided. The best-guess process flow is modeled using an inverse modeling...
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7318208 |
Method for circuit sensitivity driven parasitic extraction
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing...
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7315803 |
Verification environment creation infrastructure for bus-based systems and modules
A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model....
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7315993 |
Verification of RRAM tiling netlist
The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part”...
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7315990 |
Method and system for creating, viewing, editing, and sharing output from a design checking system
Existing text output from a design rule checker is put in appropriate input format, and automatically displayed as text within a design tool using existing design tool capabilities, such as...
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7315995 |
Semiconductor integrated circuit designing method and program
An object of the present invention is to prevent occurrence of an unconnected terminal during arrangement and connection, shorten the time required for automatic arrangement and connection, improve...
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7315996 |
Method and system for performing heuristic constraint simplification
A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the...
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7315994 |
Method and device for automated layer generation for double-gate FinFET designs
In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each...
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7315992 |
Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated...
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7313773 |
Method and device for simulator generation based on semantic to behavioral translation
Generating a simulator from an architecture description. A target architecture model described in an architecture description language (ADL) is accessed. The model comprises a semantic...
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