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7620922 |
Method and system for optimized circuit autorouting
An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit...
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7620920 |
Time separated signals
Systems, methods, and other embodiments associated with time separated signals are described. One system embodiment includes a delay circuit, two or more sets of interconnects, and a clocked...
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7620919 |
Method and system for logic equivalence checking
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on...
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7620918 |
Method and system for logic equivalence checking
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on...
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7620883 |
Techniques for mitigating, detecting, and correcting single event upset effects
SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and...
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7620853 |
Methods for detecting resistive bridging faults at configuration random-access memory output nodes
Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine...
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7620827 |
Methods and apparatus for cooling integrated circuits
A system and method are disclosed which may include measuring a leakage current level of a processor or multiprocessor chip; and storing an indicator value indicative of the leakage current level...
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7617477 |
Method for selecting and optimizing exposure tool using an individual mask error model
Methods are disclosed for selecting and optimizing an exposure tool using an individual mask error model. In one embodiment, a method includes selecting a model of a lithography process including...
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7617474 |
System and method for providing defect printability analysis of photolithographic masks with job-based automation
Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A...
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7617469 |
Assertion description conversion device, method and computer program product
An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion...
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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617466 |
Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device
A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths. The hazard check device includes a means for equivalent conversion...
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7617465 |
Method and mechanism for performing latch-up check on an IC design
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then...
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7617463 |
Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit
In a power supply port decision step, first, a required minimum number of power supply ports for use in a test is found based on power consumption information and the required minimum number of...
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7617084 |
Mechanism and method for simultaneous processing and debugging of multiple programming languages
Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and...
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7616805 |
Pattern defect inspection method and apparatus
The pattern defect inspection apparatus is operable to detect defects by comparing a detection image, which is obtained through scanning by an image sensor those patterns that have the identical...
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7614024 |
Method to implement metal fill during integrated circuit design and layout
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known...
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7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits
Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured...
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7614021 |
Optimal amplifier performance selection method
A method of determining an amplifier performance is provided. One embodiment establishes a number of amplifier performance constraints. A search is then conducted for an input and an output disk...
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7613968 |
Device and method for JTAG test
In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two...
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7613599 |
Method and system for virtual prototyping
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are...
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7610570 |
Method and mechanism for using systematic local search for SAT solving
An improved method and mechanism for designing and verifying an electrical circuit design is provided using an improved SAT-solver which uses complete assignments and systematic local search to...
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7610569 |
Chip design verification apparatus and data communication method for the same
A method of verifying a chip design includes: a software side operation step of transmitting output data generated by an operation of a software block to an interface unit, determining whether...
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7610568 |
Methods and apparatus for making placement sensitive logic modifications
Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already...
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7607116 |
Method and apparatus for verifying system-on-chip model
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification...
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7607057 |
Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic...
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7606694 |
Framework for cycle accurate simulation
A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a...
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7603647 |
Recognition of a state machine in high-level integrated circuit description language code
A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as...
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7603638 |
Method and system for modeling statistical leakage-current distribution
Disclosed is a method and system for modeling statistical leakage current distribution using logarithmic skew-normal distribution by generating statistical data with a statistical analysis method...
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7603637 |
Secure, stable on chip silicon identification
A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a...
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7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method
An assertion generating system is disclosed. In an assertion generating system 207 , a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a...
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7600212 |
Method of compensating photomask data for the effects of etch and lithography processes
A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7600209 |
Generating constraint preserving testcases in the presence of dead-end constraints
Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is...
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7600207 |
Stress-managed revision of integrated circuit layouts
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout...
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7600206 |
Method of estimating the signal delay in a VLSI circuit
A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI...
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7600204 |
Method for simulation of negative bias and temperature instability
An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned...
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7600203 |
Circuit design system and circuit design program
A circuit design system has: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class G i from the netlist; a judgment module...
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7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process
A technique for providing a product FIT rate is performed within electronic circuitry (e.g., one or more computerized devices). The technique involves receiving a Mean Time To Failure (MTTF) target...
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7599826 |
System and method for generating various simulation conditions for simulation analysis
A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module ( 301 ) for generating an N-bit binary sequence...
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7599823 |
Automated approach to resolving artificial algebraic loops
A method and apparatus for resolving artificial algebraic loops in model executions include providing a model of an executable process having a plurality of functions. An analysis step identifies...
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7596776 |
Light intensity distribution simulation method and computer program product
A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape...
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7596774 |
Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
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7596770 |
Temporal decomposition for design and verification
Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations...
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7596423 |
Method and apparatus for verifying a site-dependent procedure
The present invention includes a method of verifying a Site-Dependent (S-D) processing procedure, the method including receiving a plurality of wafers by a S-D transfer system, determining S-D...
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7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing
One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add...
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7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been...
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7594207 |
Computationally efficient design rule checking for circuit interconnect routing design
Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements...
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7594206 |
Fault detecting method and layout method for semiconductor integrated circuit
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor...
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7594205 |
Interface configurable for use with target/initiator signals
Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of...
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