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7506285 Multi-dimensional analysis for predicting RET model accuracy  
A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a...
7506286 Method and system for debugging an electronic system  
Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging...
7506281 Two-pass method for implementing a flexible testbench  
A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the...
7506287 Method, system, and program product for pre-compile processing of hardware design language (HDL) source files  
A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded...
7506283 System and method for accelerating circuit measurements  
A system for accelerating circuit measurements includes a circuit. A signal is applied to the circuit. A set of measurements is taken of a response of the circuit to the applied signal. The system...
7506280 Magnetic winding and method of making same  
The present invention provides an improved magnetic winding and method of calculating desired winding parameters (winding layer thickness, number of winding layers and number of turns per winding...
7506293 Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis  
A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected...
7506288 Interactive analysis and debugging of a circuit design during functional verification of the circuit design  
While performing functional verification on a circuit design, a verification tool allows a user to analyze the results of a previous functional analysis. The tool may also receive commands for a...
7506279 Design supporting apparatus capable of checking functional description of large-scale integrated circuit to detect fault in said circuit  
A design supporting apparatus is disclosed, including: an inputting part; a syntactic analyzing part; and a scanning and searching part. The inputting part inputs functional description data of a...
7506291 Test emulator, emulation program and method for manufacturing semiconductor device  
A test emulator for emulating a test of a semiconductor device is provided. The test emulator includes a test pattern providing means for providing a test pattern to a device simulator which...
7505766 System for determining conducted radio frequency (RF) receiver sensitivity and related methods  
A test method for determining conducted radio frequency (RF) receiver sensitivity using an RF source coupled to an RF receiver by an RF cable may include determining a bit error rate (BER) versus...
7506282 Apparatus and methods for predicting and/or calibrating memory yields  
An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of...
7506290 Method and system for case-splitting on nodes in a symbolic simulation framework  
A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more...
7503025 Method to generate circuit energy models for macros containing internal clock gating  
A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro containing internal clock gating. Circuit energy models are used to estimate system...
7502724 Test simulator, test simulation program and recording medium  
A test simulator for simulating a test of a semiconductor device is disclosed, the test simulator including: a test pattern holding unit for holding an existing test pattern to be supplied to the...
7503029 Identifying layout regions susceptible to fabrication issues by using range patterns  
A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of...
7503021 Integrated circuit diagnosing method, system, and program product  
The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the...
7503023 Efficient method for locating a short circuit  
A method of locating a short circuit of a shorted circuit path in a circuit layout includes receiving a connecting stack of the circuit layout, receiving the circuit layout defining the connecting...
7503022 Test method for unit re-modification  
The present invention described a test method for unit re-modification, in which there is a test end and a host end. The method generated a sample pattern at a test end, generates a control pattern...
7500208 Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime  
Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line...
7500209 Stage evaluation of a state machine  
The present invention provides a method and system for stage evaluation of a state machine model. Two types of transitions are used: first-stage transitions and second-stage transitions for a...
7500207 Influence-based circuit design  
An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the...
7500204 Real-time adaptive control for best IC performance  
The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into...
7500215 Method of developing application-specific integrated circuit devices  
A method, computer readable medium apparatus and system for developing an Application-Specific Integrated Circuit (“ASIC”) are disclosed. In one embodiment, a method includes defining the...
7500218 Lithographic apparatus, method, and computer program product for generating a mask pattern and device manufacturing method using same  
Grayscale Optical Proximity Correction device features are added to a mask pattern by convoluting the device features with a two-dimensional correction kernel or two one-dimensional correction...
7500206 Delay time verifying method with less processing load  
In a method of verifying a delay time of a target circuit section, a first determination of a shortest of short delay times of each of components of the target circuit section in two or more...
7500217 Handling of flat data for phase processing including growing shapes within bins to identify clusters  
Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then...
7500205 Skew reduction for generated clocks  
There is disclosed systems and processes for optimizing circuit descriptions by reducing clock skew, re-organizing and/or converting gated and generated clock circuits, and reconnecting clock nets...
7500162 Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing  
An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input...
7496872 Library creating device and interconnect capacitance estimation system using the same  
An interconnect capacitance estimation system includes a first storage device, a library creating device and an interconnect capacitance estimating device. The first storage device stores layout...
7496876 Method for generating integrated functional testcases for multiple boolean algorithms from a single generic testcase template  
One aspect of the present invention includes a method for generating functional testcases for multiple boolean algorithms from a single generic testcase template. In one embodiment, the method...
7496884 Distributed hierarchical partitioning framework for verifying a simulated wafer image  
A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the...
7496871 Mutual inductance extraction using dipole approximations  
Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal...
7496820 Method and apparatus for generating test vectors for an integrated circuit under test  
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one...
7496863 Nonlinear driver model for multi-driver systems  
A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by...
7496874 Semiconductor yield estimation  
A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant...
7496873 Method and system for determining required quantity of testing points on a circuit layout diagram  
A method and system is proposed for determining the required quantity of testing points on a circuit layout diagram generated by a computer-aided circuit layout design program on a computer...
7493247 Integrated circuit analysis system and method using model checking  
A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model...
7493240 Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithm  
Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The...
7493576 CDM ESD event protection in application circuits  
Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note...
7493578 Correlation of data from design analysis tools with design blocks in a high-level modeling system  
Methods are provided for processing design information of an electronic circuit design. A single path or multiple paths that are produced by a first design tool are an input for the method. Each...
7493574 Method and system for improving yield of an integrated circuit  
Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to...
7493577 Automatic recognition of geometric points in a target IC design for OPC mask quality calculation  
A method and system is provided for automatically recognizing geometric points of features in a target design for OPC mask quality calculation. For each feature in the target design, x, y points...
7493434 Determining the value of internal signals in a malfunctioning integrated circuit  
A method that enables testing any point (target point) within a core, including a point within a combinatorial circuit of a core, permits testing of points that are not otherwise unobservable in...
7490305 Method for driving values to DC adjusted/untimed nets to identify timing problems  
A method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized,...
7488691 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device of the present invention includes a step (S 100 ) of judging whether an interconnect pitch of an interconnect pattern having the smallest interconnect...
7490304 Determining geometrical configuration of interconnect structure  
Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method...
7490303 Identifying parasitic diode(s) in an integrated circuit physical design  
A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further...
7490307 Automatic generating of timing constraints for the validation/signoff of test structures  
An apparatus comprising a database, an input module and a software tool. The database may be configured to generate one or more database files representing a design of an integrated circuit (IC)....
7487474 Designing an integrated circuit to improve yield using a variant design element  
An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A...
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