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7558719 |
System and method for runtime analysis of system models for variable fidelity performance analysis
Systems, methods, software, and techniques can be used to provide and monitor simulation environments including one or more model components. A particular model component can have multiple...
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7558718 |
Method and system for design verification of video processing systems with unbalanced data flow
In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field...
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7559042 |
Layout evaluating apparatus
To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual...
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7558639 |
Method and apparatus for integrated hierarchical electronics analysis
A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite...
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7555416 |
Efficient transistor-level circuit simulation
Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.
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7555687 |
Sequential scan technique for testing integrated circuits with reduced power, time and/or cost
Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan...
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7555740 |
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis
Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an...
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7555294 |
System for determining total isotropic sensitivity (TIS) and related methods
A test method for determining total isotropic sensitivity (TIS) of a mobile wireless communications device including a radio frequency (RF) receiver and an antenna coupled thereto may include...
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7555741 |
Computer-aided-design tools for reducing power consumption in programmable logic devices
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a...
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7555734 |
Processing constraints in computer-aided design for integrated circuits
A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow...
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7555295 |
System for determining radiated radio frequency (RF) receiver sensitivity and related methods
A test method is described for determining radiated radio frequency (RF) receiver sensitivity may include determining a bit error rate (BER) versus traffic channel (TCH) power level function for an...
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7552406 |
Incorporation of uncertainty information in modeling a characteristic of a device
A method and model for modeling a characteristic C that is distributed within a domain. A provided base equation expresses C as a function f of a variable V through use of N+1 parameters C 0 , C 1...
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7552415 |
Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
A method for customization of the software of an FPGA-based SoC includes the steps of selecting ( 380 ) a system component used for customizing the FPGA-based SoC, configuring ( 382 ) the selected...
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7552410 |
Estimating LUT power usage
A method of calculating power usage of a lookup table (LUT) implemented on a programmable logic device can include determining input power usage of the LUT and determining output power usage of the...
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7552407 |
Method and system for performing target enlargement in the presence of constraints
A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more...
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7552411 |
LSI analysis method, LSI analysis apparatus, and computer product
In an LSI analysis apparatus, a logic element pair extracting unit extracts an unselected logic element pair when an input unit receives circuit description input. A searching unit searches for an...
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7552417 |
System for search and analysis of systematic defects in integrated circuits
Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs...
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7549134 |
Method and system for performing crosstalk analysis
Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as...
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7549135 |
Design methodology of guard ring design resistance optimization for latchup prevention
A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS...
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7549069 |
Estimating software power consumption
Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by...
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7546561 |
System and method of state point correspondence with constrained function determination
A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a...
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7546562 |
Physical integrated circuit design with uncertain design conditions
In one embodiment of the invention, a physical integrated circuit (IC) design tool is provided including a design uncertainties file, a user interface (UI) software module, and a design analysis...
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7546566 |
Method and system for verification of multi-voltage circuit design
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage...
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7543250 |
On-chip packet-based interconnections using repeaters/routers
In some embodiments, multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which...
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7543254 |
Method and apparatus for fast identification of high stress regions in integrated circuit structure
Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional...
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7542891 |
Method of correlating silicon stress to device instance parameters for circuit simulation
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard,...
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7543253 |
Method and apparatus for compensating for temperature drift in semiconductor processes and circuitry
The present invention provides a method and apparatus for compensating for temperature effects in the operation of semiconductor processes circuitry, such as reference circuits. The method operates...
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7543255 |
Method and apparatus to reduce random yield loss
One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors...
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7543263 |
Automatic trace shaping method
An automatic trace shaping method comprises the steps of: setting sets of coaxial equiangular octagons each having sides parallel with a predetermined reference line; performing a process for...
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7543257 |
Apparatus for giving assistance in analyzing deficiency in RTL-input program and method of doing the same
An apparatus for giving assistance in analyzing deficiency in a RTL-input program, includes a partial RTL creator which creates partial RTL description data containing logic description identical...
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7543251 |
Method and apparatus replacing sub-networks within an IC design
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
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7539957 |
Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks
Methods and apparatus for testing integrated circuits are provided. Integrated circuits sometimes contain repeating blocks of identical circuitry. Each identical circuit block contains scan chain...
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7539893 |
Systems and methods for speed binning of integrated circuits
Methods and apparatus sort integrated circuits by maximum operating speed (f max ). The timing for a first set of critical timing paths is statistically characterized. The first set can be, for...
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7539968 |
Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints
An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy...
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7539958 |
Estimation of average-case activity for digital circuits
The present invention provides a method for estimating the average-case activity in a digital circuit. The method includes the steps of assigning initial activity values to outputs of flops in the...
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7539956 |
System and computer program product for simultaneous cell identification/technology mapping
A system, method and computer program product are provided for simultaneous cell identification/technology mapping. In use, a plurality of data operators is received. Further, at least two cells...
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7539960 |
Reducing a parasitic graph in moment computation algorithms in VLSI systems
An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is...
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7539552 |
Method and apparatus for implementing a universal coordinate system for metrology data
A method includes receiving a metrology report including metrology data collected by a metrology tool, position data associated with the metrology data, and context data associated with the...
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7539959 |
Library creating apparatus and method, and recording medium recording library creating program thereon
In order to efficiently create a library of characteristic values of a low hierarchical circuit, which library is used in operation verification of circuitry including low hierarchical circuitry...
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7536662 |
Method for recognizing and verifying FIFO structures in integrated circuit designs
First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural...
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7536615 |
Logic analyzer systems and methods for programmable logic devices
A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for...
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7536670 |
Method for verifying and choosing lithography model
A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration...
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7536663 |
Method and apparatus for quantifying the timing error induced by an impedance variation of a signal path
In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the...
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7533356 |
Parameter adjusting device and parameter adjusting means
A parameter adjusting device and a parameter adjusting method configured to adjust a great number of parameters used for a circuit design model of a semiconductor element such as a transistor...
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7533357 |
Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis
A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution...
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7533358 |
Integrated sizing, layout, and extractor tool for circuit design
Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of...
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7531368 |
In-line lithography and etch system
The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer...
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7529294 |
Testing of multiple asynchronous logic domains
A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator...
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7530036 |
Random test generation using an optimization solver
An optimization process is repeatedly invoked over an input, which includes the set of constraints and the objective function. The input of each invocation is randomly modified, so as to cause the...
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7529655 |
Program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language
According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event...
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