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7574334 |
Formal methods for modeling and analysis of hybrid systems
A technique based on the use of a quantifier elimination decision procedure for real closed fields and simple theorem proving to construct a series of successively finer qualitative abstractions of...
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7574682 |
Yield analysis and improvement using electrical sensitivity extraction
A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension...
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7574681 |
Method and system for evaluating computer program tests by means of mutation analysis
Methods and systems for evaluating computer program tests by mutation analysis, including the execution of mutated programs with the insertion of mutations and the identification of mutated...
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7571399 |
Process for checking the quality of the metallization of a printed circuit
The invention relates to a process for checking the quality of the metallization of a printed circuit, and also includes the printed circuits produced. According to the invention, the checking...
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7570539 |
Method for identifying memory bit cells and connections
A method for identifying memory bit cells and connections for analysis of a circuit block. The method includes defining a bit pattern for each bit cell node in a bit cell. The method also includes...
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7571398 |
Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits
A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated...
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7571402 |
Scan chain modification for reduced leakage
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
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7571397 |
Method of design based process control optimization
The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout...
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7571406 |
Clock tree adjustable buffer
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of...
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7571087 |
Computer storage exception handling apparatus and method for virtual hardware system
In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples,...
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7571405 |
Electrical design rule checking expert traverser system
Method and apparatus for rule checking systems that validate an electronic design is disclosed. Generally, information is extracted from a plurality of nodes in a netlist and stored for a set of...
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7571407 |
Semiconductor integrated circuit and method of testing delay thereof
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
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7571401 |
Calculating distortion summaries for circuit distortion analysis
Methods for analyzing circuit distortion based on contributions from separate circuit elements are presented. Local approximations that do not require high-order derivatives of device models are...
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7571400 |
Chip design verifying and chip testing apparatus and method
A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a...
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7571422 |
Method for generating a design rule map having spatially varying overlay budget
The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if...
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7568174 |
Method for checking printability of a lithography target
A technique for determining, without having to perform optical proximity correction, when the result of optical proximity correction will fail to meet the design requirements for printability. A...
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7568173 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration
Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in...
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7567892 |
Method and system for realizing a logic model design
Techniques directed to realizing and verifying a logic model design are provided by first dividing the logic model design into two or more logic portions. The various model portions can then...
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7567891 |
Hot-carrier device degradation modeling and extraction methodologies
The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of...
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7567893 |
Clock simulation system and method
A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock...
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7567894 |
Monitoring physical parameters in an emulation environment
A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time,...
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7568175 |
Ramptime propagation on designs with cycles
A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime...
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7568006 |
e-Business on-demand for design automation tools
Methods, apparatus and articles of manufacture are disclosed for a design automation application to evaluate a design automation task using an on-demand computer network. A requesting entity...
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7565635 |
SiP (system in package) design systems and methods
SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module...
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7565636 |
System for performing verification of logic circuits
The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of...
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7565633 |
Verifying mask layout printability using simulation with adjustable accuracy
A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the...
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7565634 |
Massively parallel boolean satisfiability implication circuit
The application concerns prototyped custom Programmable Logic Devices (Pills) for Boolean satisfiability (SAT) problems. This approach is based on the use of clause evaluation circuits (CECs),...
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7562330 |
Budgeting global constraints on local constraints in an autorouter
Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a...
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7562322 |
Design verification for a switching network logic using formal techniques
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the...
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7562315 |
Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an...
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7560946 |
Method of acceptance for semiconductor devices
A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric...
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7562319 |
Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects
Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A...
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7562320 |
Asic based conveyor belt style programmable cross-point switch hardware accelerated simulation engine
An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication...
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7561999 |
Verification apparatus, verification method, and program
A verification apparatus that efficiently performs hardware verification and software verification in the development of a system LSI with great accuracy. At the hardware verification, an...
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7562318 |
Test structure for automatic dynamic negative-bias temperature instability testing
The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI)....
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7562321 |
Method and apparatus for structured ASIC test point insertion
Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the...
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7559041 |
Method and apparatus for designing semiconductor integrated circuit
A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit...
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7559043 |
Library test circuit and library test method
A library test circuit for verifying functions of a plurality of standard cell library logic cells includes a core module including a plurality of standard cell library logic cells, each logic cell...
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7558719 |
System and method for runtime analysis of system models for variable fidelity performance analysis
Systems, methods, software, and techniques can be used to provide and monitor simulation environments including one or more model components. A particular model component can have multiple...
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7558718 |
Method and system for design verification of video processing systems with unbalanced data flow
In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field...
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7559042 |
Layout evaluating apparatus
To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual...
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7558639 |
Method and apparatus for integrated hierarchical electronics analysis
A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite...
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7555416 |
Efficient transistor-level circuit simulation
Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.
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7555687 |
Sequential scan technique for testing integrated circuits with reduced power, time and/or cost
Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan...
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7555740 |
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis
Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an...
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7555294 |
System for determining total isotropic sensitivity (TIS) and related methods
A test method for determining total isotropic sensitivity (TIS) of a mobile wireless communications device including a radio frequency (RF) receiver and an antenna coupled thereto may include...
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7555741 |
Computer-aided-design tools for reducing power consumption in programmable logic devices
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a...
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7555734 |
Processing constraints in computer-aided design for integrated circuits
A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow...
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7555295 |
System for determining radiated radio frequency (RF) receiver sensitivity and related methods
A test method is described for determining radiated radio frequency (RF) receiver sensitivity may include determining a bit error rate (BER) versus traffic channel (TCH) power level function for an...
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7552406 |
Incorporation of uncertainty information in modeling a characteristic of a device
A method and model for modeling a characteristic C that is distributed within a domain. A provided base equation expresses C as a function f of a variable V through use of N+1 parameters C 0 , C 1...
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