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7610570 |
Method and mechanism for using systematic local search for SAT solving
An improved method and mechanism for designing and verifying an electrical circuit design is provided using an improved SAT-solver which uses complete assignments and systematic local search to...
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7610569 |
Chip design verification apparatus and data communication method for the same
A method of verifying a chip design includes: a software side operation step of transmitting output data generated by an operation of a software block to an interface unit, determining whether...
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7606694 |
Framework for cycle accurate simulation
A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a...
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7607057 |
Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic...
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7607116 |
Method and apparatus for verifying system-on-chip model
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification...
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7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method
An assertion generating system is disclosed. In an assertion generating system 207 , a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a...
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7603637 |
Secure, stable on chip silicon identification
A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a...
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7603638 |
Method and system for modeling statistical leakage-current distribution
Disclosed is a method and system for modeling statistical leakage current distribution using logarithmic skew-normal distribution by generating statistical data with a statistical analysis method...
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7603647 |
Recognition of a state machine in high-level integrated circuit description language code
A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7600204 |
Method for simulation of negative bias and temperature instability
An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned...
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7600212 |
Method of compensating photomask data for the effects of etch and lithography processes
A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to...
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7600209 |
Generating constraint preserving testcases in the presence of dead-end constraints
Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is...
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7600203 |
Circuit design system and circuit design program
A circuit design system has: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class G i from the netlist; a judgment module...
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7599823 |
Automated approach to resolving artificial algebraic loops
A method and apparatus for resolving artificial algebraic loops in model executions include providing a model of an executable process having a plurality of functions. An analysis step identifies...
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7600206 |
Method of estimating the signal delay in a VLSI circuit
A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI...
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7600207 |
Stress-managed revision of integrated circuit layouts
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout...
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7599826 |
System and method for generating various simulation conditions for simulation analysis
A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module ( 301 ) for generating an N-bit binary sequence...
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7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process
A technique for providing a product FIT rate is performed within electronic circuitry (e.g., one or more computerized devices). The technique involves receiving a Mean Time To Failure (MTTF) target...
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7596423 |
Method and apparatus for verifying a site-dependent procedure
The present invention includes a method of verifying a Site-Dependent (S-D) processing procedure, the method including receiving a plurality of wafers by a S-D transfer system, determining S-D...
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7596776 |
Light intensity distribution simulation method and computer program product
A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape...
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7596770 |
Temporal decomposition for design and verification
Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations...
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7596774 |
Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
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7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been...
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7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing
One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add...
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7594207 |
Computationally efficient design rule checking for circuit interconnect routing design
Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements...
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7594206 |
Fault detecting method and layout method for semiconductor integrated circuit
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor...
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7594205 |
Interface configurable for use with target/initiator signals
Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of...
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7590955 |
Method and system for implementing layout, placement, and routing with merged shapes
Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are...
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7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid
A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference...
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7590968 |
Methods for risk-informed chip layout generation
A chip layout is generated based on a quantified fabrication process capability. A minimum required value is selected for a fabrication process capability factor associated with a fabrication...
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7590912 |
Using a chip as a simulation engine
The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and...
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7590953 |
Static timing analysis and dynamic simulation for custom and ASIC designs
A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the...
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7590958 |
Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities
A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing...
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7590954 |
Test solution development method
A test solution for one or more circuits implementing a communication standard is based on a design specification received from a development organization and a communication standard. The test...
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7590957 |
Method and apparatus for fixing best case hold time violations in an integrated circuit design
The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to...
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7587689 |
Method of supporting wiring design, supporting apparatus using the method, and computer-readable recording medium
A method of supporting an optimum wiring design of a linear structure, includes steps of providing a finite element model of both of the linear structure and a support member which supports the...
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7587688 |
User-directed timing-driven synthesis
Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori...
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7586299 |
Power-supply semiconductor integrated circuit, power-supply semiconductor integrated circuit system, development assisting system for power-supply circuit, and program and storage medium therefor
There is provided a power-supply platform IC for realizing a parameter-deciding power-supply circuit, which, in order to decide a parameter of a power-supply circuit that supplies power to an...
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7587692 |
Method and apparatus for full-chip thermal analysis of semiconductor chip designs
A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design...
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7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction
One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which...
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7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets
The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing...
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7587690 |
Method and system for global coverage analysis
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and...
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7586322 |
Test structure and method for measuring mismatch and well proximity effects
The present invention is directed to a test structure and method to determine the effects of the well proximity effect on the gate threshold voltage of FETs at different distances from the edge of...
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7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a...
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7584077 |
Physical design characterization system
A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site...
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7584442 |
Method and apparatus for generating memory models and timing database
A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each...
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7584438 |
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout...
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7584439 |
Cell modeling for integrated circuit design with characterization of upstream driver strength
A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A...
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7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
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