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7302651 |
Technology migration for integrated circuits with radical design restrictions
A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are...
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7302653 |
Probability of fault function determination using critical defect size map
Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical...
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7299446 |
Enabling efficient design reuse in platform ASICs
A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and...
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7299431 |
Method for tracing paths within a circuit
A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a...
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7299427 |
Radio prototyping system
A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide...
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7299429 |
System and method for providing burst licensing in a circuit simulation environment
A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the...
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7299430 |
Reducing design execution run time bit stream size for device testing
A method of testing a programmable logic device (PLD) can include distinguishing between stages within the design that uniquely test a routing resource and stages that do not. The method also can...
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7299428 |
Model stamping matrix check technique in circuit simulator
The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining...
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7299435 |
Frequency dependent timing margin
A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the...
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7299447 |
Method of testing a mapping of an electrical circuit
An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable instruction sets are predefined for...
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7299432 |
Method for preserving constraints during sequential reparameterization
A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs,...
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7296247 |
Method and apparatus to improve pass transistor performance
A control circuit generates a temperature-dependent gate voltage for turning on a transistor. For NMOS transistors, the gate voltage is increased in response to decreases in temperature to...
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7296249 |
Using constrained scan cells to test integrated circuits
Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan...
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7296250 |
Method and system for characterizing electronic circuitry
According to the invention a characteristic property of an electronic circuit component depending on at least one variable (X 1 , X 2 ) is approximated by an approximating function. This is...
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7293248 |
System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis
There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least...
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7290227 |
Method of calibrating semiconductor line width
A method of calibrating a line width in a semiconductor device including fitting line width CD (critical dimension) data to a log function by measuring the line width CD data to plot selectively...
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7290230 |
System and method for verifying a digital design using dynamic abstraction
A method for verifying a digital system design is provided. A first abstraction of a digital system design is performed to obtain an abstract model of the digital system design. One or more first...
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7290228 |
Hardware accelerator with a single partition for latches and combinational logic
A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred...
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7290229 |
Method and system for optimized handling of constraints during symbolic simulation
A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing...
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7287235 |
Method of simplifying a circuit for equivalence checking
A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a...
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7287238 |
Method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation
The present invention is directed to a method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation. Addresses may be provided to...
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7284176 |
Externally-loaded weighted random test pattern compression
The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.
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7282942 |
Enhanced sampling methodology for semiconductor processing
The present invention improves wafer sampling methods by partitioning a semiconductor wafer into a set of sampling regions and calculating yield of a sampling region(s) of the semiconductor wafer.
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7284210 |
Method for reconfiguration of random biases in a synthesized design without recompilation
A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver...
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7284212 |
Minimizing computational complexity in cell-level noise characterization
Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and...
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7284213 |
Defect analysis using a yield vehicle
A system and method for collecting and analyzing optical inspection results obtained during the manufacturing process and comparing those results to actual functional results of a specially...
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7284217 |
Method of LSI designing and a computer program for designing LSIS
An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a...
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7283942 |
High speed techniques for simulating circuits
The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called...
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7284216 |
System and method for verifying signal propagation delays of circuit traces of a PCB layout
A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer ( 1 ). The computer includes: a setting module ( 10 ) for setting a...
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7281225 |
Circuit verification using multiple engines
In one embodiment, a method for circuit verification using multiple engines includes running multiple traces on a circuit using multiple reachability algorithms, selecting an effective reachability...
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7281224 |
Wide geometry recognition by using circle-tangent variable spacing model
Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in...
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7281223 |
System and method for modeling an integrated circuit system
The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method...
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7281222 |
System and method for automatic generation of optical proximity correction (OPC) rule sets
A method of automatically creating and/or optimizing an optical proximity correction (OPC) rule set can include providing an initial OPC rule set and applying the initial OPC rule set to a layout...
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7281136 |
LSI design method and verification method
An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design...
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7277840 |
Method for detecting bus contention from RTL description
A method for efficiently detecting bus contention from a register transfer level (RTL) description is provided. A bus contention occurs if more than two components try to propagate data onto a bus...
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7278123 |
System-level test architecture for delivery of compressed tests
An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of...
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7277965 |
Apparatus and methods for the automated creation of distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in...
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7275226 |
Method of performing latch up check on an integrated circuit design
A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within...
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7275078 |
Distributed web CGI architecture
A distributed web CGI architecture is disclosed. According to one embodiment of the present invention, distributed web common gateway interface architecture includes a primary network having a...
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7275231 |
High level validation of designs and products
A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a...
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7275225 |
Correcting design data for manufacture
A method of correction for design data includes the steps of sequentially applying a plurality of corrections to a plurality of features based on a plurality of feature tolerances to design data in...
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7272801 |
System and method for process-flexible MEMS design and simulation
A system-level design and simulation environment utilizing a process specification tool that is programmatically integrated with the system level design and simulation environment thereby enabling...
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7272807 |
Determining equivalent waveforms for distorted waveforms
An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced...
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7269810 |
Global equivalent circuit modeling system for substrate mounted circuit components incorporating substrate dependent characteristics
The present invention is a substrate dependent circuit modeling system for substrate-mounted components. The height and dielectric constant of a substrate have a significant impact on the frequency...
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7269809 |
Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits
Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate...
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7269804 |
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution...
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7269816 |
Driven inspection or measurement
Design driven inspection/metrology methods and apparatus are provided. A recipe is a set of instructions including wafer processing parameters, inspection parameters, or control parameters for...
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7269811 |
Method of and apparatus for specifying clock domains in electronic circuit designs
A method of specifying clock domains in electronic circuit designs in a system level design tool is disclosed. The method generally comprises steps of providing a design having a plurality of...
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7269807 |
Area ratio/occupancy ratio verification method and pattern generation method
Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed...
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7266795 |
System and method for engine-controlled case splitting within multiple-engine based verification framework
A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of...
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