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7325209 |
Using patterns for high-level modeling and specification of properties for hardware systems
This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language...
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7322016 |
Impact checking technique
A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is in...
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7322017 |
Method for verification using reachability overapproximation
A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design,...
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7322015 |
Simulating a dose rate event in a circuit design
Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The...
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7319947 |
Method and apparatus for performing distributed simulation utilizing a simulation backplane
A method and apparatus for performing distributed simulation is presented. According to an embodiment of the present invention, simulators are interfaced to a simulation backplane via...
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7320115 |
Method for identifying a physical failure location on an integrated circuit
A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or...
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7320116 |
Method of generating cell library data for large scale integrated circuits
A method of generating library data for a cell constructed of interconnected MOS transistors, includes a resistance extraction step which extracts source and drain resistances according to source...
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7320114 |
Method and system for verification of soft error handling with application to CMT processors
A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is...
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7318204 |
Synthesizing semiconductor process flow models
Systems and methods of modeling a best-guess semiconductor process flow for fabricating a desired semiconductor device are provided. The best-guess process flow is modeled using an inverse modeling...
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7318206 |
Offset determination for measurement system matching
Dynamic offset determination for each of a plurality of measurement systems for matching the systems is disclosed. One embodiment uses an artifact which is periodically run across the measurement...
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7318012 |
Problem solving method utilizing emergent clustering and case retrieval
An Adaptive, Any-Time Case Retrieval process combines existing knowledge (emergent clustering, case retrieval with CRN) in a novel and advantageous way. Although ideally suited to the Digital Body...
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7318205 |
Measure of analysis performed in property checking
The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false...
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7315993 |
Verification of RRAM tiling netlist
The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part”...
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7315996 |
Method and system for performing heuristic constraint simplification
A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the...
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7313781 |
Image data correction method, lithography simulation method, image data correction system, program, mask and method of manufacturing a semiconductor device
An image data correction method includes preparing correction data for correcting a distortion of an image obtained by an image acquiring section, acquiring outline data of a desired pattern...
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7313509 |
Simulation method and apparatus, and computer-readable storage medium
A simulation method makes a noise analysis based on parameters including a conductor resistance which takes skin effect into consideration. The simulation method calculates a first resistance of...
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7313771 |
Computing current in a digital circuit based on an accurate current model for library cells
In one embodiment, a method for computing current in a digital circuit based on an accurate current model for library cells includes accessing a cell library, for each cell in the cell library...
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7313770 |
MOSFET modeling for IC design accurate for high frequencies
The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a...
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7310792 |
Method and system for modeling variation of circuit parameters in delay calculation for timing analysis
A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in...
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7310791 |
Method for correcting layout errors
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least...
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7310595 |
Numerically modeling inductive circuit elements
A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces...
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7310788 |
Sample probability of fault function determination using critical defect size map
Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical...
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7310789 |
Use of overlay diagnostics for enhanced automatic process control
Disclosed are apparatus and methods for obtaining and analyzing various unique metrics or “target diagnostics” from one or more semiconductor overlay targets. In one embodiment, an overlay...
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7310795 |
Method and apparatus for simulating logic circuits that include a circuit block to which power is not supplied
A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which...
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7310785 |
Video processing architecture definition by function graph methodology
A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H. 264 specification or other such...
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7310594 |
Method and system for designing a multiprocessor
A multiprocessor system ( 10 ) includes a plurality of processing engines ( 14, 16, 18, 20, 22, 32, 33 and 35 ) including a software processing engine and a hardware processing engine implemented...
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7308657 |
Method for generating hints for program analysis
The present invention provides a method, apparatus and article of manufacture for generating hints for use when performing reach-ability analysis of a program such as programmatic representations...
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7308658 |
Method and apparatus for measuring test coverage
A method, computer program product, and data processing system for determining test sequences' coverage of events in testing a semiconductor design are disclosed. Test patterns are randomly...
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7308656 |
Method and apparatus for generating a boundary scan description and model
An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through...
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7308395 |
Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group
According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a...
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7308659 |
Apparatus and method for RTL modeling of a register
The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are...
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7308662 |
Capacitance modeling
A method of modeling capacitance for all practical 2D on-chip wire structures including coplanar and microstrip structures. The method includes using a field lines approach ( 600 ) to obtain...
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7308660 |
Calculation system of fault coverage and calculation method of the same
A calculation system of fault coverage includes a data acquiring module acquiring layout information and gate net data, a layout analysis and fault link module extracting a layout element...
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7305636 |
Method and system for formal unidirectional bus verification using synthesizing constrained drivers
A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level...
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7305637 |
Efficient SAT-based unbounded symbolic model checking
An efficient approach for SAT-based quantifier elimination and pre-image computation using unrolled designs that significantly improves the performance of pre-image and fix-point computation in...
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7305638 |
Method and system for ROM coding to improve yield
A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two...
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7305632 |
Method for designing arithmetic device allocation
An arithmetic device allocation design method of the present invention includes the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased...
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7305633 |
Distributed configuration of integrated circuits in an emulation system
Data processing resources are distributively provided to an emulation system to locally and correspondingly configure emulation integrated circuits. In certain embodiments the data processing...
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7305635 |
Serial implementation of assertion checking logic circuit
Serial assertion checking is realized in a System On a Chip (SoC) device by connecting scan chain output to a bit extractor configured within a functionally reconfigurable module that is part of...
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7305634 |
Method to selectively identify at risk die based on location within the reticle
A method and system of selectively identifying at risk die based on location within the reticle. Reticle and stepping information is stored in a database. All reticle shots in a wafer and in a lot...
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7304721 |
Method for dynamically monitoring a reticle
The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle deposits or electrostatically...
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7302663 |
Automatic antenna diode insertion for integrated circuits
Automatic antenna diode insertion for integrated circuits is described. In an example, at least a portion of an integrated circuit is defined by a block of standard cells selected from a cell...
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7302380 |
Simulation apparatus, method and program
A simulation apparatus for simulating a pipeline processor including a pipeline simulation unit and an instruction simulation unit. The simulation apparatus includes a pipeline simulation unit is...
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7302652 |
Leakage control in integrated circuits
Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an...
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7302654 |
Method of automating place and route corrections for an integrated circuit design from physical design validation
A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit...
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7302656 |
Method and system for performing functional verification of logic circuits
A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by...
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7302655 |
Method for verifying a circuit design by assigning numerical values to inputs of the circuit design
A method for verifying a circuit design includes a step of assigning numerical values 1/a i to input ports of the circuit design according to a function a i+1 =(a i −1) 2 +1, wherein i...
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7302658 |
Methods for evaluating quality of test sequences for delay faults and related technology
In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so...
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7302375 |
Simulation of processes, devices and circuits by a modified newton method
Roughly described, a method for numerically solving a system of equations of the form
0= F ( X ),
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7302668 |
Layout designing/characteristic analyzing apparatus for a wiring board
A layout designing/characteristic analyzing apparatus for a wiring board includes a module library memory for storing in advance for each of wiring board modules which are constituents of the...
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