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7386817 |
Method of determining stopping powers of design structures with respect to a traveling particle
A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a...
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7386776 |
System for testing digital components
In order to test digital modules with functional elements, these are divided into test units ( 3 ) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of...
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7386815 |
Test yield estimate for semiconductor products created from a library
Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are...
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7386820 |
Method and apparatus for formally checking equivalence using equivalence relationships
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM DFG and HLM DFG . RTLM DFG and HLM DFG are then put into...
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7386816 |
Method for manufacturing an electronic device having an electronically determined physical test member
A method for manufacturing an electronic device such as an integrated circuit or display device is provided. A design description of the electronic device is generated using a computer aided design...
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7383521 |
Characterization and reduction of variation for integrated circuits
A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process...
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7383518 |
Method and apparatus for performance metric compatible control of data transmission signals
The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a...
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7383519 |
Systems and methods for design verification using selectively enabled checkers
Systems and methods for performing design verification testing in which test cases are analyzed to determine the characteristics that will be verified in a module under test, and in which the...
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7383520 |
Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs
A method and apparatus for optimizing cooling system performance using full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for optimizing the...
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7383523 |
Semiconductor integrated circuit
To provide a semiconductor integrated circuit in which a clock signal supplied to each flip-flop will not be adversely affected when a functional change is made using a spare flip-flop. The...
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7380227 |
Automated correction of asymmetric enclosure rule violations in a design layout
Automated techniques may correct certain rule violations, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic...
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7380224 |
Method and system for non-linear state based satisfiability
A computerized method and system for solving non-linear Boolean equations is disclosed comprising at least partially solving a Boolean function; developing at least one inference regarding said...
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7380228 |
Method of associating timing violations with critical structures in an integrated circuit design
A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit...
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7380225 |
Method and computer program for efficient cell failure rate estimation in cell arrays
A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An...
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7380226 |
Systems, methods, and apparatus to perform logic synthesis preserving high-level specification
A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one...
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7376918 |
Probabilistic noise analysis
A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the...
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7376916 |
Performing a constrained optimization to determine circuit parameters
One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated...
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7376917 |
Client-server semiconductor verification system
A client-server semiconductor verification system is described. The system comprises a client device storing a test job having test vectors and configuration data for programmable logic for testing...
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7376544 |
Vector transfer during co-simulation
Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling...
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7376919 |
Methods and apparatuses for automated circuit optimization and verification
Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and...
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7373622 |
Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements
An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform...
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7373631 |
Methods of producing application-specific integrated circuit equivalents of programmable logic
Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively...
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7373216 |
Method and apparatus for verifying a site-dependent wafer
The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing...
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7373618 |
Method and system for selection and replacement of subcircuits in equivalence checking
A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method...
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7373620 |
Methods and mechanisms for extracting and reducing capacitor elements
A method of extracting capacitance from a layout record includes imposing voltages on conductors in a layout record, and determining a total charge for each of the conductors to obtain a capacitor...
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7373623 |
Method and apparatus for locating circuit deviations
A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by...
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7373619 |
Post-silicon test coverage verification
In one embodiment, the invention is directed to a method of optimizing post-silicon test coverage for a system under test (“SUT”). The method comprises defining coverage data comprising...
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7373621 |
Constraint-driven test generation for programmable logic device integrated circuits
A programmable logic device test generation tool is provided that produces test configuration data and test vectors for testing programmable logic device integrated circuits. A graph generation...
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7370292 |
Method for incremental design reduction via iterative overapproximation and re-encoding strategies
A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a...
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7370299 |
Method and computer program product for register transfer level power estimation in chip design
A method for register transfer level power estimation in chip design includes the steps of: (A) parsing all possible condition branches of conditional statements in a register transfer level code,...
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7370298 |
Method for heuristic preservation of critical inputs during sequential reparameterization
A method, system, and computer program product for preserving critical inputs. According to an embodiment of the present invention, an initial design including one or more primary inputs which...
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7370296 |
Modeling language and method for address translation design mechanisms in test generation
Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A...
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7370300 |
Systems and methods of simulating signal coupling
Systems and methods for simulating signal coupling in electronic devices are disclosed. In an exemplary implementation a computer program product executes a computer process to simulate a victim...
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7370297 |
Method, system, and computer program for validating correspondence information between behavior and lower level description of a circuit design
A circuit design support method, system, and computer program product for displaying information on a circuit information described according to each design level in circuit design is described....
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7370311 |
Generating components on a programmable device using a high-level language
Methods and apparatus are provided for implementing a programmable device including a processor core and a hardware accelerator. A portion of a program written in a high-level language is...
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7370310 |
Static address mapping
Address map generation is described. More particularly, static addresses are obtained. A system design at least a portion of which is for instantiation in configurable logic of an integrated...
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7369697 |
Process variable of interest monitoring and control
Methods for monitoring and controlling process variables of interest during the substrate manufacturing process is provided. Numerical estimates for selected attributes of a feature of interest may...
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7367001 |
Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals
A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design,...
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7367002 |
Method and system for parametric reduction of sequential designs
A method, system and computer program product for performing parametric reduction of sequential designs. According to an embodiment of the present invention, the method includes receiving an...
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7366652 |
Method of programming a co-verification system
A co-verification system includes a computer programmed to act as a simulator for simulating behavior of a first portion of an electronic device under test (DUT) by acquiring, processing and...
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7366650 |
Software and hardware simulation
A verification environment is provided that co-verifies a software component 8 and a hardware component 10 . Within the same environment using a common test controller 18 both hardware stimuli...
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7366651 |
Co-simulation interface
Method and apparatus for interfacing between a high-level modeling system and a hardware description language (HDL) co-simulation engine. A plurality of HDL co-simulation engine libraries are...
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7367000 |
Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program
The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for...
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7366648 |
Electronic circuit analyzing apparatus, electronic circuit analyzing method, and electronic circuit analyzing program
The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic...
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7366998 |
Efficient communication of data between blocks in a high level modeling system
A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is...
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7363202 |
State exploration using multiple state groupings
Exploration algorithms are relevant to the industrial practice of generating test cases from an abstract state machine whose runs define the predicted behavior of the software system under test....
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7363604 |
Accurate noise modeling in digital designs
A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output...
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7363602 |
Computer-supported, automated method for the verification of analog circuits
The invention relates to a computer-supported, automated method for the verification of analog circuits, and to a storage medium on which a computer software program is stored for performing such...
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7363596 |
Methods for storing and naming static library cells for lookup by logic synthesis and the like
A method is provided for creating and using a library of known logic elements for facilitating the design of equivalent FPGA, structured ASIC, or other integrated circuits. Each cell in the library...
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7363605 |
Eliminating false positives in crosstalk noise analysis
A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and...
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