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7409650 |
Low power consumption designing method of semiconductor integrated circuit
In a standard cell synthesizing step 101 , a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance...
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7409654 |
Method and apparatus for performing test pattern autograding
A method, computer program product, and data processing system for minimizing the number of test sequences needed to achieve a desired level of coverage of events in testing a semiconductor design...
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7409656 |
Method and system for parallelizing computing operations
Disclosed is an improved method and system for implementing parallel processing of computing operations by effectively handling dependencies between different sequences of computing operations. In...
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7409669 |
Automatic test configuration generation facilitating repair of programmable circuits
Techniques are provided that control the generation of test routes to improve the ability of a test system to isolate defects on programmable circuits. A test generator creates test routes that...
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7409667 |
Techniques for modeling a circuit board structure
A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit board dimension parameters from a...
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7409655 |
Method of designing semiconductor integrated circuit and apparatus for designing the same
A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the...
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7409651 |
Automated migration of analog and mixed-signal VLSI design
A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source technology. The source circuit includes...
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7409668 |
Method for improving via's impedance
A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of:...
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7409648 |
Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit
The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores...
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7409665 |
Method for checking return path of printed and CAD apparatus for designing patterns of printed board
A CAD apparatus designing patterns of a printed board. The apparatus includes a signal wiring pattern detecting unit for detecting a signal wiring pattern, and a guard ground detecting unit for...
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7406405 |
Method and system for design verification using proof-based abstraction
A design verifier includes a bounded model checker, an abstractor and an unbounded model checker. The bounded model checker verifies a property to a depth K and either finds a counterexample, or...
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7406670 |
Testing of an integrated circuit having an embedded processor
Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of...
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7404171 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
System and method for configuring semiconductor functional circuits
The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational...
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7404159 |
Critical area computation of composite fault mechanisms using Voronoi diagrams
Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi...
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7404157 |
Evaluation device and circuit design method used for the same
There is provided an evaluation apparatus capable of measuring the I-V characteristic in the MOSFET AC operation with a high accuracy. There are also provided a circuit design method and a circuit...
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7404160 |
Method and system for hardware based reporting of assertion information for emulation and hardware acceleration
A method and system for hardware based reporting of assertion information for emulation and hardware acceleration is disclosed. In one embodiment, a method of performing assertion-based...
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7404158 |
Inspection method and inspection apparatus for semiconductor integrated circuit
In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit including plural transistors according to which a test pattern generated for the...
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7400157 |
Composite wiring structure having a wiring block and an insulating layer with electrical connections to probes
A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data...
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7401009 |
Magnetostatic modeling methods and systems for use with boundary element modeling
Methods and systems for magnetostatic modeling of a magnetic object is disclosed. A varying surface charge density is established at a surface of a magnetic object modeled by a magnetostatic model....
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7401304 |
Method and apparatus for thermal modeling and analysis of semiconductor chip designs
A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design...
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7399648 |
Methods and apparatus for determining location-based on-chip variation factor
Techniques for determining a location-based on-chip variation factor for an integrated circuit device are provided. A first on-chip variation factor is computed for at least one of two or more...
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7401309 |
Integrated circuit hierarchical design system, integrated circuit hierarchical design program and integrated circuit hierarchical design method
An integrated circuit hierarchical design system for optimizing a circuit locating between flip-flops included in a lower layer through a higher layer among layers forming an integrated circuit,...
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7401066 |
Correlation of end-of-line data mining with process tool data mining
One embodiment of the present invention is a process tool optimization system that includes: (a) a data mining engine that analyzes end-of-line yield data to identify one or more process tools...
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7401305 |
Adaptive application of SAT solving techniques
A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search...
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7401307 |
Slack sensitivity to parameter variation based timing analysis
A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With...
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7401317 |
Method and system for rapidly identifying silicon manufacturing defects
The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first...
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7398445 |
Method and system for debug and test using replicated logic
A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into...
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7398492 |
Rules and directives for validating correct data used in the design of semiconductor products
A method to validate data used in a design of a semiconductor product. The method includes (a) reading resources of an application set defining the semiconductor product in a partially fabricated...
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7398494 |
Method for performing verification of logic circuits
The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and...
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7398497 |
Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method
An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general...
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7398424 |
False path detection program
A false path detection program whereby passing points of signal lines constituting false paths are directly detected, thereby shortening the processing time necessary for the false path detection...
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7398485 |
Yield optimization in router for systematic defects
Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify...
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7398493 |
Isolated pwell tank verification using node breakers
A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where...
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7398503 |
Method and apparatus for pre-tabulating sub-networks
A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network based on the...
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7398489 |
Advanced standard cell power connection
A method for establishing standard cell power connections is disclosed. The method generally includes the steps of (A) calculating a power consumption of a plurality of logic cells receiving power...
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7398490 |
Digital circuit layout techniques using binary decision diagram for identification of input equivalence
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the...
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7398504 |
Program, method and apparatus for analyzing transmission signals
From design information on a circuit board a wiring designation unit designates a wiring model for signal analysis. A first analysis unit generates, through a 3-D electromagnetic analysis, a first...
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7398491 |
Method for fast incremental calculation of an impact of coupled noise on timing
A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC...
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7395518 |
Back end of line clone test vehicle
A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer ( 1902 ). The one or...
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7395519 |
Electronic-circuit analysis program, method, and apparatus for waveform analysis
A design-change-target-circuit detecting unit inputs circuit information including an element model describing an electronic circuit to detect an electronic circuit using a changed element model. A...
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7395516 |
Manufacturing aware design and design aware manufacturing
Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration....
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7392490 |
System and method of modelling capacitance of on-chip coplanar transmission line structures over a substrate
Methods, systems and apparatus for modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the...
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7392169 |
Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language
According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event...
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7392489 |
Methods and apparatus for implementing application specific processors
Methods and apparatus are provided for efficiently implementing an application specific processor. An application specific processor includes a data path and a control path. A control path is...
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7392168 |
Method of compensating for etch effects in photolithographic processing
A computer system reads data corresponding to an IC layout target layer and performs an etch simulation on the target layer. Etch biases are calculated and the inverse of the etch biases are used...
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7389215 |
Efficient presentation of functional coverage results
A method for presentation of functional coverage includes representing a set of attributes of a design under test as a multi-dimensional cross-product space, which includes events corresponding to...
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7389482 |
Method and apparatus for analyzing post-layout timing violations
A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a...
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7389480 |
Content based yield prediction of VLSI designs
A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit...
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7389481 |
Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells
A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific...
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7386819 |
Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e.g., a programmed FPGA LUT) is verified for such functional equivalence by using...
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