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7620942 |
Method and system for parameterization of imperative-language functions intended as hardware generators
A method ( 100 ) of translating an imperative language function into a parameterized hardware component can include the steps of using ( 102 ) formal imperative function arguments to represent at...
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7620918 |
Method and system for logic equivalence checking
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on...
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7619521 |
RFID network configuration program
An RFID network design system comprising a website hosted on a host computer which generates and displays icons specifically directed to various RFID components of a RFID network on a computer...
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7617535 |
Infected electronic system tracking
Techniques for generating an access control list to block traffic from a network device infected by malware.
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7614029 |
Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric
Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and...
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7613944 |
Programmable local clock buffer capable of varying initial settings
A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer...
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7610570 |
Method and mechanism for using systematic local search for SAT solving
An improved method and mechanism for designing and verifying an electrical circuit design is provided using an improved SAT-solver which uses complete assignments and systematic local search to...
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7610567 |
Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs
Methods and systems automate an approach to provide a way to convert a circuit design from a synchronous representation to an asynchronous representation without any designer or user interaction or...
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7610566 |
Method and apparatus for function decomposition
Some embodiments provide a method of performing circuit synthesis that receives a design that has a function with several inputs. The method identifies a set of early arriving inputs of the...
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7606774 |
Computer implemented cover process approximating quantifier elimination
A computer implemented cover process is disclosed for use in program analysis and verification techniques where existential quantifier elimination is not possible. The cover process allows an...
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7603647 |
Recognition of a state machine in high-level integrated circuit description language code
A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as...
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7603635 |
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same
A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7596770 |
Temporal decomposition for design and verification
Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations...
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7594204 |
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A...
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7594201 |
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated...
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7594195 |
Multithreaded reachability
In one embodiment, a method for multithreaded reachability analysis includes partitioning a state space of a circuit under analysis into a plurality of partitions and assigning each partition to a...
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7587688 |
User-directed timing-driven synthesis
Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori...
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7587687 |
System and method for incremental synthesis
A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to...
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7584460 |
Process and apparatus for abstracting IC design files
File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to...
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7584449 |
Logic synthesis of multi-level domino asynchronous pipelines
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a...
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7577929 |
Early timing estimation of timing statistical properties of placement
A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation...
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7574684 |
Design data creating method, design data creating apparatus and computer readable information recording medium
A design data creating method, for creating design data to which predetermined design constraint requirements are added, includes a display data converting step of converting input design...
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7568173 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration
Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in...
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7565636 |
System for performing verification of logic circuits
The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of...
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7565632 |
Behavioral synthesizer system, operation synthesizing method and program
A behavioral synthesis system which synthesizes behavior without inline expansion of a callee function, even one which has a pointer as an argument during the synthesis of a caller function. There...
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7565631 |
Method and system for translating software binaries and assembly code onto hardware
A computer-aided hardware design system enables design of an actual hardware implementation for a digital circuit using a software implementation of an algorithm in assembly language or machine...
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7562322 |
Design verification for a switching network logic using formal techniques
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the...
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7562317 |
Multitasking circuit layout diagram silkscreen text handling method and system
A multitasking circuit layout diagram silkscreen text handling method and system is proposed, which is designed for use in conjunction with a computer platform that runs a CAD (Computer-Aided...
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7555739 |
Method and apparatus for maintaining synchronization between layout clones
A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method...
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7552405 |
Methods of implementing embedded processor systems including state machines
Methods of implementing state machines using embedded processors. The designer specifies the logical footprint of the state machine in a formalism that can be transformed into hardware. This...
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7546566 |
Method and system for verification of multi-voltage circuit design
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage...
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7546565 |
Method for comparing two designs of electronic circuits
A method implemented as a computer program product for comparing two designs of electronic circuits, wherein the design representations comprise several hierarchically related sheets. The method...
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7546561 |
System and method of state point correspondence with constrained function determination
A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a...
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7546560 |
Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist
A method for optimizing a design of a circuit is disclosed. The method generally includes the steps of (A) identifying a plurality of first flip flops in the design and (B) replacing each of the...
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7543253 |
Method and apparatus for compensating for temperature drift in semiconductor processes and circuitry
The present invention provides a method and apparatus for compensating for temperature effects in the operation of semiconductor processes circuitry, such as reference circuits. The method operates...
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7543252 |
Migration of integrated circuit layout for alternating phase shift masks
Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to...
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7539956 |
System and computer program product for simultaneous cell identification/technology mapping
A system, method and computer program product are provided for simultaneous cell identification/technology mapping. In use, a plurality of data operators is received. Further, at least two cells...
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7539955 |
System and method for reformatting a motherboard design file
A method for reformatting a motherboard design file includes the steps of: converting the motherboard design file from a first format to a second format, and generating a converted temp file based...
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7539953 |
Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system
Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is...
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7530047 |
Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the...
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7530037 |
Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods
A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor...
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7529858 |
Hard disk drive controller having versatile chip connector having printed circuit board engaged by at least two data ports having two pairs of differential connector elements
A hard disk controller (HDC) chip has interchangeable “A” and “B” ports of differential connector element pairs, with one connector element of each pair being disposed closest to the edge...
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7523423 |
Method and apparatus for production of data-flow-graphs by symbolic simulation
One embodiment of the present invention provides a system that produces a non-canonical data flow graph (DFG) structure by symbolic simulation of an input representation for a high-level model...
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7523421 |
Method and apparatus for reducing the cost of multiplexer circuitry
Methods and apparatus are provided for reducing the cost of multiplexer circuitry. Electrically equivalent data inputs and corresponding multiplexers can be eliminated from a multiplexer cone. A...
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7519939 |
Method and program for supporting register-transfer-level design of semiconductor integrated circuit
A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a...
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7519930 |
Method of calculating a model formula for circuit simulation
A circuit simulator for a semiconductor device with reduced channel length includes a method of calculating a model formula for circuit simulation of a semiconductor device; calculating first...
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7516430 |
Generating testcases based on numbers of testcases previously generated
A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or...
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7516425 |
Method for generating minimal leakage current input vector using heuristics
A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics includes transforming the integrated circuit to a logic representation with PMOS...
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7516060 |
Circuit-level memory and combinational block modeling
A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations...
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