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6553562 |
Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques
A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying “horizontal” critical features and...
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6553560 |
Alleviating line end shortening in transistor endcaps by extending phase shifters
One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by...
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6553558 |
Integrated circuit layout and verification method
A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the...
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6550051 |
Lithographic data verification method and photo mask manufacturing method
To reduce the time for verification in lithographic data and reduce the turn-around-time in preparation of lithographic data, a first lithographic input data and a second lithographic input data...
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6548312 |
Manufacturing method of semiconductor integrated circuit devices and mask manufacturing methods
In order to inhibit or prevent a pattern abnormality such as the deformation or misalignment of a pattern of a semiconductor integrated circuit device, a light intensity is calculated based on the...
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6546543 |
Method of displaying, inspecting and modifying pattern for exposure
According to a menu item selected in step S 12 (a pressed command button), for a wafer exposing pattern, program goes to steps S 13 and S 14, and further, display in step S 15, inspection in...
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6546544 |
Method of producing mask data for partial one-shot transfer exposure and exposure method
A method of producing mask data for partial one-shot transfer (block) exposure suitable for fabrication of an integrated circuit such as a system LSI in small numbers, in many models and with a...
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6543044 |
Method of extracting characters and computer-readable recording medium
Using the hierarchy cell 5 , cell 51 , cell 52 , cell 4 of the figure cells in the design pattern data, it is not necessary to take the actual forms of patterns and the arrangement information of...
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6543045 |
Method for detecting and automatically eliminating phase conflicts on alternating phase masks
A method for eliminating phase conflicts that occur in the layout of a phase mask in a localized and automated manner. The method includes a first step in which a set of phase conflicts is...
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6539331 |
Microscopic feature dimension measurement system
A measurement tool connects to an automatic inspection machine for measuring microscopic characteristics of features on a photographic mask. Widths of densely packed lines are measured for features...
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6539521 |
Dissection of corners in a fabrication layout for correcting proximity effects
A technique for forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, includes identifying evaluation points on an edge of a...
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6539276 |
Semiconductor circuit having surface features and method of adjusting a tool with respect to this surface
A semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly...
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6537738 |
System and method for making smooth diagonal components with a digital photolithography system
A digital photolithography system is provided that is capable of making smooth diagonal components. The system includes a computer for providing a first digital pattern to a digital pixel panel,...
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6536032 |
Method of processing exposure mask-pattern data, simulation using this method, and recording medium
Disclosed herein is a method of processing exposure mask-pattern data. The method comprises the steps of performing a re-sizing process of adding a prescribed positive bias Δ to design data of an...
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6530074 |
Apparatus for verification of IC mask sets
A method of fabricating an IC includes forming a test circuit in/on the wafer to electrically indicate that a correct mask set was used during a revision of the IC design during the manufacturing...
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6524752 |
Phase shift masking for intersecting lines
Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension...
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6523164 |
Method and apparatus for modifying flattened data of designed circuit pattern
Grouping is performed by classifying the data of features having same shapes and sizes in the same layer into the same group. In the grouping, a feature size having lengths of two adjacent sides of...
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6523163 |
Method for forming pattern data and method for writing a photomask with additional patterns
A method for writing a photomask with additional patterns for making a photomask having uniform pattern density is provided, wherein the method for writing a photomask with additional patterns can...
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6519759 |
Photomask pattern shape correction method and corrected photomask
To provide a photomask pattern shape correction method for suitably modifying and correcting a pattern deformation caused by a optical proximity effect. A corner 1 is extracted where an exterior...
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6519758 |
Method of checking exposure patterns formed over photo-mask
The present invention provides a method of checking exposure patterns with reference to checking data, and the exposure patterns having an overlapping region receiving double-exposures of electron...
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6519760 |
Method and apparatus for minimizing optical proximity effects
Optical proximity effects (OPEs) are a well-known phenomenon in photolithography. OPEs result from the structural interaction between the main feature and neighboring features. It has been...
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6516459 |
Integrated circuit design correction using fragment correspondence
Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle to a target layout, while backward mapping refers to mapping of...
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6516452 |
Method and apparatus for verifying design data
Disclosed is an apparatus for comparing CAD (computer aided design) design data comprising one or more components with a set of design rules generated relative said components and generating an...
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6516448 |
Fiber aligning structure
The present invention relates to a device for passively aligning at least one substrate-carried optical fiber with at least one optical device. The substrate is patterned with a buried etching stop...
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6513151 |
Full flow focus exposure matrix analysis and electrical testing for new product mask evaluation
A method for new product mask evaluation is provided. Focus exposure matrices are printed at one or more layers (e.g., active gate) on full flow production wafers. The focus exposure matrices are...
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6507944 |
Data processing method and apparatus, reticle mask, exposing method and apparatus, and recording medium
A data processing apparatus comprises a grid pattern area calculation section ( 24 ) for calculating the minimum grid and the present area of a circuit element for each layer of circuit patterns...
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6499003 |
Method and apparatus for application of proximity correction with unitary segmentation
The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity...
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6499135 |
Computer aided design flow to locate grounded fill in a large scale integrated circuit
For an integrated circuit having multiple metal layers, a computer-aided design (CAD) method for designing grounded fill in the integrated circuit includes: (a) finding the eligible fill areas for...
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6496973 |
Method for designing mask pattern of a self scanning light emitting device
A method of designing an optimum mask pattern for forming a metal line by an etching process, the metal line also effectively serving as a light-shielding layer, is provided. In this method,...
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6492066 |
Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion
A method ( 100 ) of characterizing optical proximity correction designs includes performing a mathematical transform ( 160 ) on a first feature ( 150 ) and a second feature ( 167 ) each having a...
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6493866 |
Phase-shift lithography mapping and apparatus
For phase-shifting microlithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes assigning a first phase to a first...
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6493867 |
Digital photolithography system for making smooth diagonal components
A digital photolithography system is provided that is capable of making smooth diagonal components. The system includes a computer for providing a first digital pattern to a digital pixel panel,...
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6487712 |
Method of manufacturing mask for conductive wirings in semiconductor device
Disclosed is a method of manufacturing a mask for conductive wirings in a semiconductor device, wherein the conductive wirings are formed on a semiconductor substrate of the semiconductor device,...
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6485871 |
Method of producing phase masks in an automated layout generation for integrated circuits
A method of producing phase masks for automatically generating a layout for an integrated circuit includes the step of compacting a layout of an integrated circuit by processing a distance graph. A...
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6484306 |
Multi-level scanning method for defect inspection
A method for performing scanned defect inspection of a collection of contiguous areas using a specified false-alarm-rate and capture-rate within an inspection system that has characteristic seek...
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6484307 |
Method for fabricating and checking structures of electronic circuits in a semiconductor substrate
A method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate. By using two different masks, in two method steps, identical configurations of...
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6483120 |
Control system for a charged particle exposure apparatus
A control system is provided for a charged particle exposure apparatus. A plurality of dot control data are concatenated and compressed to generate compressed concatenated control data. A plurality...
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6477700 |
Reticle having discriminative pattern narrower in pitch than the minimum pattern width but wider than minimum width in the pattern recognition
A reticle has a main pattern to be transferred to a photo-sensitive layer and surrounded by a non-transparent layer, and a discriminative pattern loops in the non-transparent layer so as to define...
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6470489 |
Design rule checking system and method
A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The...
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6467076 |
Method and apparatus for submicron IC design
The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag...
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6463577 |
Method of manufacturing mask using independent pattern data files
There are independently made data of a device pattern, an identification and scribe pattern including a scribe pattern surrounding the device pattern, identification patterns formed in a scribe...
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6456893 |
Apparatus management system
A machine management system improves flexibility in control of an apparatus and installation of an additional apparatus. A plurality of refrigerators sends operational information to a virtual...
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6457169 |
Geometric phase analysis for overlay measurement
A method of measuring overlay error comprises forming a first mask having a first alignment array comprising a periodic pattern of first features having a first periodicity, forming a second mask...
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6457168 |
Method for producing structures on the surface of a semiconductor wafer
The invention relates to a method for producing structures on the surface of a semiconductor wafer, in which after the generation of a primary layout corresponding to the structures to be produced...
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6453458 |
System and method for generating a flat mask design for projecting a circuit pattern to a spherical semiconductor device
The present invention provides a method for segmenting and mapping a two-dimensional conventional circuit pattern to a flat mask for projection onto a three-dimensional surface. The circuit pattern...
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6453274 |
Method of forming a pattern using proximity-effect-correction
A method of correcting light proximity effects includes the steps of: compressing design data of a circuit pattern (step S 1 ); generating a projection image which is formed during a process of...
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6446252 |
Photomask method for making the same capacitor cell area near outmost cell arrays
A method for manufacturing a photomask of cylindrical capacitor arrays surrounded by a corrugated protection trench is provided. First, a capacitor array layout is generated, next, the capacitor...
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6425117 |
System and method for performing optical proximity correction on the interface between optical proximity corrected cells
The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to...
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6421815 |
Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions
Finite state machines (FSMs) are synthesized from hierarchical high-level descriptions and optimized. Partitions of the FSM are selected by scanning the nodes of the hierarchical description and...
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6421820 |
Semiconductor device fabrication using a photomask with assist features
A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4 A) based on normalized feature spacing. Before the device...
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