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7620931 |
Method of adding fabrication monitors to integrated circuit chips
An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit...
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7620930 |
Method, program product and apparatus for model based scattering bar placement for enhanced depth of focus in quarter-wavelength lithography
A method of generating a mask is provided that optimizes the placement and shape of optical proximity correction (OPC) features such as scattering bars. According to some aspects, the method...
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7617478 |
Flash-based anti-aliasing techniques for high-accuracy high efficiency mask synthesis
One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process....
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7617476 |
Method for performing pattern pitch-split decomposition utilizing anchoring features
A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of: (a) determining a minimum critical dimension and...
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7617473 |
Differential alternating phase shift mask optimization
A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width....
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7614031 |
Drawing apparatus with drawing data correction function
A data correcting apparatus is for correcting drawing data representing a drawing pattern included in a quadrangular drawing area of a drawing subject. The correction process is based on an ideal...
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7604912 |
Local flare correction
A correction of a local flare generated at a time of exposure when manufacturing a semiconductor device, wherein a substantial numerical aperture to a pattern in a region to be exposed is...
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7603648 |
Mask design using library of corrections
Systems, techniques, and approaches to quickly generate mask patterns, synthesize near-fields, and design masks. In one aspect, a mask may be designed by modeling the transmitted field using a...
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7600213 |
Pattern data verification method, pattern data creation method, exposure mask manufacturing method, semiconductor device manufacturing method, and computer program product
A pattern data verification method includes preparing exposure data related to a circuit pattern to be formed on a substrate, calculating a characteristic of an image of an exposure pattern on a...
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7598005 |
Photomask and manufacturing method of the same, and pattern forming method
Data (pattern data) ( 21 ) of a mask data ( 2 ) to form a mask pattern is made into an octagon. An electron-beam lithography system has a high resolution, and it requires a polygonal pattern data...
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7596776 |
Light intensity distribution simulation method and computer program product
A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape...
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7596420 |
Device manufacturing method and computer program product
A method is provided wherein a lithographic projection apparatus is used to print a series of test patterns on a test substrate to measure printed critical dimension as function of exposure dose...
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7589819 |
Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems
Provided is a method and system for developing a lithographic mask layout. The lithographic mask layout is adapted for configuring an array of micro-mirrors in a maskless lithography system. The...
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7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets
The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing...
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7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a...
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7572557 |
Non-collinear end-to-end structures with sub-resolution assist features
Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two...
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7571424 |
Diffused aerial image model semiconductor device fabrication
A lithography method has a simulation method for mathematically approximating a photoresist film pattern with a Diffused Aerial Image Model (“DAIM”) for semiconductor device fabrication. The...
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7571423 |
Optimized photomasks for photolithography
Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process,...
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7571417 |
Method and system for correcting a mask pattern design
A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired...
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7569310 |
Sub-resolution assist features for photolithography with trim ends
Sub-resolution assist features with trim ends are described for use in photolithography. A photolithography mask with elongated features is synthesized. A sub-resolution assist feature is applied...
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7565639 |
Integrated assist features for epitaxial growth bulk tiles with compensation
A method for making a semiconductor device is provided which comprises (a) creating a first data set ( 301 ) which defines a first set of tiles ( 303 ) for a trench chemical mechanical polishing...
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7562336 |
Contrast based resolution enhancement for photolithographic processing
A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to...
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7562333 |
Method and process for generating an optical proximity correction model based on layout density
A method ( 300 ) for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask ( 310 ) having a plurality of symmetric...
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7549141 |
Photomask, photomask manufacturing method, and photomask processing device
A photomask is manufactured by a method including providing a substrate having a surface on which a predetermined pattern is to be formed, positioning the substrate in an exposure tool so as to...
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7543252 |
Migration of integrated circuit layout for alternating phase shift masks
Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to...
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7537864 |
Hole pattern design method and photomask
A method of designing hole patterns for arranging hole patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing, wherein a grid...
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7533363 |
System for integrated circuit layout partition and extraction for independent layout processing
A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide...
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7530049 |
Mask manufacturing system, mask data creating method and manufacturing method of semiconductor device
A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method...
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7526749 |
Methods and apparatus for designing and using micro-targets in overlay metrology
Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first...
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7512928 |
Sub-resolution assist feature to improve symmetry for contact hole lithography
A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features...
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7512927 |
Printability verification by progressive modeling accuracy
A fast method of verifying a lithographic mask design is provided wherein catastrophic errors are identified by iteratively simulating and verifying images for the mask layout using progressively...
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7509624 |
Method and apparatus for modifying a layout to improve manufacturing robustness
One embodiment of the present invention provides a system that modifies a layout to improve manufacturing robustness. During operation, the system receives a layout. The system then selects a...
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7509621 |
Method and apparatus for placing assist features by identifying locations of constructive and destructive interference
One embodiment of the present invention provides a system that determines a location in a layout to place an assist feature. During operation, the system receives a layout of an integrated circuit....
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7509620 |
Dual phase shift photolithography masks for logic patterning
A pair of phase shift photolithography masks and a process for deriving them is described. In one embodiment, the invention includes deriving a complex electric field estimate for an intended...
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7505884 |
Method for automatic generation of finite element mesh from IC layout data
The present invention includes a method for performing a thermal analysis, including the steps of determining size and placement of each of a plurality of drivers on an integrated circuit device....
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7500219 |
Exposure data generator and method thereof
A plurality of patterns placed within an target region are classified by their placement positions, a pattern adjacent to each side of each pattern is searched for by using the classification...
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7496884 |
Distributed hierarchical partitioning framework for verifying a simulated wafer image
A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the...
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7496883 |
Method and apparatus for identifying and correcting phase conflicts
One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable....
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7496880 |
Method and apparatus for assessing the quality of a process model
One embodiment of the present invention provides a system that assesses the quality of a process model. During operation, the system receives a mask layout and additionally receives a process model...
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7488937 |
Method and apparatus for the improvement of material/voltage contrast
A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved...
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7487474 |
Designing an integrated circuit to improve yield using a variant design element
An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A...
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7475382 |
Method and apparatus for determining an improved assist feature configuration in a mask layout
One embodiment of the present invention provides a system that determines the locations and dimensions of one or more assist features in an uncorrected or corrected mask layout. During operation,...
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7475379 |
Methods and systems for layout and routing using alternating aperture phase shift masks
Methods for performing phase-correct layout and routing of integrated circuits using alternating aperture phase shift masks (AltPSM), including bright field AltPSM and dark field AltPSM are...
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7473495 |
Method of creating predictive model, method of managing process steps, method of manufacturing semiconductor device, method of manufacturing photo mask, and computer program product
A method of creating a predictive model of a process proximity effect comprises: preparing a predictive model of a process proximity effect including a non-determined parameter; and determining the...
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7472368 |
Method for implementing vertically coupled noise control through a mesh plane in an electronic package design
A method is provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of...
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7465525 |
Reticle alignment and overlay for multiple reticle process
A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout...
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7461367 |
Modifying merged sub-resolution assist features of a photolithographic mask
Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting sub-resolution assist feature intersects a...
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7458045 |
Silicon tolerance specification using shapes as design intent markers
Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of...
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7454739 |
Method and apparatus for determining an accurate photolithography process model
One embodiment of the present invention provides a system that determines an accurate process model. During operation, the system receives process data. Next, the system receives an optical model...
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7451429 |
Computer automated method for optimizing an integrated circuit pattern in a layout verification process
A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks...
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