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7620926 |
Methods and structures for flexible power management in integrated circuits
Structures and methods of efficiently implementing power management in integrated circuits (ICs). An IC includes columns of logic blocks and columns of power management blocks (PMBs). The columns...
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7620922 |
Method and system for optimized circuit autorouting
An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit...
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7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective...
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7619521 |
RFID network configuration program
An RFID network design system comprising a website hosted on a host computer which generates and displays icons specifically directed to various RFID components of a RFID network on a computer...
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7617471 |
Processor event interface for programmable integrated circuit based circuit designs
A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A...
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7613942 |
Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuits
In one embodiment, a method for power mode transition in a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit includes clustering logic cells in the circuit to a number of...
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7613599 |
Method and system for virtual prototyping
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are...
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7610573 |
Implementation of alternate solutions in technology mapping and placement
A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of...
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7610566 |
Method and apparatus for function decomposition
Some embodiments provide a method of performing circuit synthesis that receives a design that has a function with several inputs. The method identifies a set of early arriving inputs of the...
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7610565 |
Technology migration for integrated circuits with radical design restrictions
A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are...
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7607114 |
Designer's intent tolerance bands for proximity correction and checking
A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into...
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7607113 |
Wiring pattern determination method and computer program product thereof
A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions...
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7607112 |
Method and apparatus for performing metalization in an integrated circuit process
A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that...
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7606774 |
Computer implemented cover process approximating quantifier elimination
A computer implemented cover process is disclosed for use in program analysis and verification techniques where existential quantifier elimination is not possible. The cover process allows an...
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7606692 |
Gate-level netlist reduction for simulating target modules of a design
A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules...
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7603645 |
Calibration method of insulating washer in circuit board
A calibration method of insulating washer in a circuit board is provided, which includes steps of (a) establishing an equivalent circuit model corresponding to a metal via; (b) depicting an...
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7603641 |
Power/ground wire routing correction and optimization
A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a...
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7596769 |
Simulation of power domain isolation
Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL)...
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7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing
One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add...
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7594212 |
Automatic pin placement for integrated circuits to aid circuit board design
A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus...
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7594211 |
Methods and apparatuses for reset conditioning in integrated circuits
Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred...
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7594206 |
Fault detecting method and layout method for semiconductor integrated circuit
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor...
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7594203 |
Parallel optimization using independent cell instances
The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes...
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7594202 |
Optimization of circuit designs using a continuous spectrum of library cells
The present invention comprises a method of optimizing a circuit design having a plurality of library cells. In one embodiment, the method includes the steps of providing a plurality of logically...
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7594201 |
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated...
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7594200 |
Method for finding multi-cycle clock gating
An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The...
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7594199 |
Method of optical proximity correction design for contact hole mask
Disclosed concepts include a method of optimizing an illumination profile of a pattern to be formed in a surface of a substrate. Illumination is optimized by defining a transmission cross...
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7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid
A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference...
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7590955 |
Method and system for implementing layout, placement, and routing with merged shapes
Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are...
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7587693 |
Apparatus and method of delay calculation for structured ASIC
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a...
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7587687 |
System and method for incremental synthesis
A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to...
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7584449 |
Logic synthesis of multi-level domino asynchronous pipelines
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a...
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7584445 |
Sequence-pair creating apparatus and sequence-pair creating method
A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block b i in a block set B and information of block placement, creates a...
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7584440 |
Method and system for tuning a circuit
The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit...
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7581197 |
Relative positioning of circuit elements in circuit design
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
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7577932 |
Gate modeling for semiconductor fabrication process effects
In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic...
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7577929 |
Early timing estimation of timing statistical properties of placement
A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation...
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7571422 |
Method for generating a design rule map having spatially varying overlay budget
The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if...
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7571420 |
Dynamic sampling with efficient model for overlay
The present invention describes a method including: determining field-clustering scheme; selecting initial sample plan; establishing initial model of overlay, the initial model of overlay...
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7571404 |
Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise
A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network...
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7571397 |
Method of design based process control optimization
The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout...
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7571396 |
System and method for providing swap path voltage and temperature compensation
The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes...
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7568179 |
Layout printability optimization method and system
A layout printability optimization method and system is presented that may be used for enhancing the manufacturability and yield of integrated circuits. The method is based on a mathematical...
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7565634 |
Massively parallel boolean satisfiability implication circuit
The application concerns prototyped custom Programmable Logic Devices (Pills) for Boolean satisfiability (SAT) problems. This approach is based on the use of clause evaluation circuits (CECs),...
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7565632 |
Behavioral synthesizer system, operation synthesizing method and program
A behavioral synthesis system which synthesizes behavior without inline expansion of a callee function, even one which has a pointer as an argument during the synthesis of a caller function. There...
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7565631 |
Method and system for translating software binaries and assembly code onto hardware
A computer-aided hardware design system enables design of an actual hardware implementation for a digital circuit using a software implementation of an algorithm in assembly language or machine...
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7562325 |
Device to cluster Boolean functions for clock gating
A system for clustering Boolean functions for clock gating according to various exemplary embodiments can include a computer configured to identify at least two small gating groups within a clock...
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7562322 |
Design verification for a switching network logic using formal techniques
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the...
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RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry
An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer...
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7559045 |
Database-aided circuit design system and method therefor
A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage...
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