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7424694 Integrated circuit layout device, method thereof and program thereof  
A layout device for an integrated circuit executes calculating a timing value with respect to each wiring path by a analysis based on connection information and delay information of wirings,...
7424655 Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits  
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective...
7421674 Apparatus and method for analyzing post-layout timing critical paths  
A critical path detecting unit for detecting critical paths for a design in which cells are placed on an integrated circuit and information concerning timing constraints. A...
7418690 Local searching techniques for technology mapping  
Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to...
7418675 System and method for reducing the power consumption of clock systems  
A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells...
7415681 Optimal mapping of LUT based FPGA  
A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form...
7415682 Automatic adjustment of optimization effort in configuring programmable devices  
User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored...
7415683 Method and apparatus for a chaotic computing module  
A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately...
7415679 System and method for selecting MOSFETs suitable for a circuit design  
The present invention provides a computer-based method for selecting MOSFETs suitable for a circuit design. The method includes the steps of: providing a database ( 18 ) that stores specifications...
7412670 Method and apparatus for optimizing distributed multiplexed bus interconnects  
Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized,...
7412675 Hierarchical feature extraction for electrical interaction  
A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a...
7412677 Detecting reducible registers  
Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition....
7412668 Integrated system noise management—decoupling capacitance  
A method for noise suppression for a system implementation of an integrated circuit design is described. First clock operating parameters for logic blocks of the integrated circuit design are...
7409650 Low power consumption designing method of semiconductor integrated circuit  
In a standard cell synthesizing step 101 , a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance...
7409658 Methods and systems for mixed-mode physical synthesis in electronic design automation  
Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections...
7409655 Method of designing semiconductor integrated circuit and apparatus for designing the same  
A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the...
7409651 Automated migration of analog and mixed-signal VLSI design  
A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source technology. The source circuit includes...
7409668 Method for improving via's impedance  
A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of:...
7404162 Buffering technique using structured delay skewing  
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design...
7404155 Merging multiplexers to reduce ROM area  
Systems and method for reducing the die area occupied by a programmable logic device are provided. The systems and methods relate to a programmable logic device comprising a plurality of...
7404154 Basic cell architecture for structured application-specific integrated circuits  
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is...
7401303 Method and apparatus for minimizing weighted networks with link and node labels  
A method and apparatus are provided for optimizing finite state machines with labeled nodes. Under the method, labels from the nodes are shifted onto the labels of the links connected to the nodes....
7401307 Slack sensitivity to parameter variation based timing analysis  
A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With...
7401318 Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes  
The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may...
7398505 Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout  
An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit...
7398497 Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method  
An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general...
7398485 Yield optimization in router for systematic defects  
Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify...
7398501 System and method for optimizing an integrated circuit design  
The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and...
7398484 Memory efficient array transposition via multi pass tiling  
A schedule can be generated for physically transposing an array such that when the array is transferred from a first memory type to a second memory type, the number of block transfers performed is...
7398507 Method of automatic synthesis of sequential quantum Boolean circuits  
A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum...
7398503 Method and apparatus for pre-tabulating sub-networks  
A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network based on the...
7398490 Digital circuit layout techniques using binary decision diagram for identification of input equivalence  
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the...
7398483 Design verification method for programmable logic design  
A technique for checking a logic design for compliance with a set of design rules in a computer-aided logic design system. An initial logic design is provided in computer-readable form in a logic...
7392499 Placement of input/output blocks of an electronic design in an integrated circuit  
Approaches for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit are disclosed. The electronic design includes at least one input/output bus...
7389478 System and method for designing a low leakage monotonic CMOS logic circuit  
A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic...
7389481 Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells  
A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific...
7389001 Reorganizing rectangular layout structures for improved extraction  
Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a...
7386585 Systems and methods for storage area network design  
Systems and methods for designing storage area network fabric. Preferably included are an arrangement for collecting user requirements on data flows to be supported by the fabric, an arrangement...
7386814 Translation of high-level circuit design blocks into hardware description language  
Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is...
7386433 Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout  
One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a...
7383524 Structure for storing a plurality of sub-networks  
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
7383526 Cost-optimization method  
A method of controlling an optimal cost is proposed, which can be applied to a circuitry designing process for making electronic products, allowing a user in drawing a circuitry to choose elements...
7383518 Method and apparatus for performance metric compatible control of data transmission signals  
The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a...
7382912 Method and apparatus for performing target-image-based optical proximity correction  
A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of...
7383520 Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs  
A method and apparatus for optimizing cooling system performance using full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for optimizing the...
7380233 Method of facilitating integrated circuit design using manufactured property values  
An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry ( 110 ). The method utilizes one or more library...
7379855 Method and apparatus for timing modeling  
Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information...
7380223 Method and system for converting netlist of integrated circuit between libraries  
The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and...
7380221 Method and system for reduction of and/or subexpressions in structural design representations  
A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial...
7380231 Wire spreading through geotopological layout  
The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing....
Matches 201 - 250 out of 1432 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >