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7480604 |
Method of modeling and producing an integrated circuit including at least one transistor and corresponding integrated circuit
A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing...
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7478344 |
Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms
A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a...
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7478355 |
Input/output circuits with programmable option and related method
A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a...
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7475381 |
Shallow trench avoidance in integrated circuits
Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.
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7475366 |
Integrated circuit design closure method for selective voltage binning
Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an...
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7475372 |
Methods for computing Miller-factor using coupled peak noise
A method for computing a Miller-factor compensated for peak noise provided. The method includes mapping at least two delays as function of at least two Miller-factors; determining an equation of...
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7472360 |
Method for implementing enhanced wiring capability for electronic laminate packages
A method is provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit...
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7472359 |
Behavioral transformations for hardware synthesis and code optimization based on Taylor Expansion Diagrams
A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated...
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7472365 |
Method for computing hold and setup slack without pessimism
The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not...
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7472362 |
Method of minimizing phase noise
A method of minimizing phase noise is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second...
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7469398 |
IP placement validation
A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information...
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7469395 |
Wiring optimizations for power
An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a...
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7467362 |
Failure detection improvement apparatus, failure detection improvement program, failure detection improvement method
A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to...
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7463547 |
Micro computer and method of optimizing microcomputer
A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to...
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7462914 |
Semiconductor circuit device and simulation method of the same
A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at...
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7464348 |
Method and system for mapping source elements to destination elements as interconnect routing assignments
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for...
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7464345 |
Resource estimation for design planning
A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the...
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7464358 |
Method for resolving overloads in autorouting physical interconnections
Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved...
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7464363 |
Verification support device, verification support method, and computer product
A verification support device supports logic verification of a design object corresponding to modified sequence diagrams obtained by modifying sequence diagrams expressing processes of a design...
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7461361 |
Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method
There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch...
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7461362 |
Replacing circuit design elements with their equivalents
Some embodiments provided a method of designing a configurable IC. The method includes receiving a first design that has at least one controllable circuit that is initialized by a first type of...
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7458041 |
Circuit optimization with posynomial function F having an exponent of a first design parameter
Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design...
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7458040 |
Resettable memory apparatuses and design
Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of...
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7458049 |
Aggregate sensitivity for statistical static timing analysis
A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution...
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7458053 |
Method for generating fill and cheese structures
A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component;...
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7458050 |
Methods to cluster boolean functions for clock gating
A method to cluster Boolean functions for clock gating according to various exemplary embodiments can include identifying at least two small gating groups within a clock tree representative of an...
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7454738 |
Synthesis approach for active leakage power reduction using dynamic supply gating
A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A...
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7454324 |
Selection of initial states for formal verification
A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification...
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7454732 |
Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs
Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a...
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7454721 |
Method, apparatus and computer program product for optimizing an integrated circuit layout
A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact...
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7454720 |
Method for optimizing a layout of supply lines
A method for optimizing a circuit layout is provided which optimizes a circuit layout as a result of utilizing unused tracks of the circuit layout to expand supply lines. In a first step, a circuit...
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7451427 |
Bus representation for efficient physical synthesis of integrated circuit designs
A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the...
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7451411 |
Integrated circuit design system
The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein...
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7448010 |
Methods and mechanisms for implementing virtual metal fill
A method for implementing virtual metal fill includes inserting metal fill data into a layout record based on one or more rules, extracting capacitance from the layout record to create a...
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7448009 |
Method of leakage optimization in integrated circuit design
This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells,...
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7444603 |
Transformation of graphs representing an electronic design in a high modeling system
Methods and apparatus are provided for processing an electronic design in a high level modeling system. A first graph is generated, with the nodes representing basic elements of the electronic...
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7441216 |
Applying CNF simplification techniques for SAT-based abstraction refinement
The present embodiment keeps track of a set of resolution required for generating each one of the clauses added by the simplification method. This information is used by the method that generates...
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7441211 |
Gate-length biasing for digital circuit optimization
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a...
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7437690 |
Method for predicate-based compositional minimization in a verification environment
A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more...
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7437691 |
VLSI artwork legalization for hierarchical designs with multiple grid constraints
A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid...
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7437689 |
Interconnect model-order reduction method
An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is...
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7434179 |
Design and simulation methods for electrostatic protection circuits
A physical analysis (S 2 ) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are...
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7430726 |
System for delay reduction during technology mapping in FPGA
The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel...
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7428713 |
Accelerated design optimization
A system, method, and software product for an accelerated design optimization is described. Engineers/designers/users define an initial design with a set of responses and constraints on the...
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7428715 |
Hole query for functional coverage analysis
Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set...
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7428712 |
Design optimization using approximate reachability analysis
Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using...
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7426668 |
Performing memory built-in-self-test (MBIST)
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more...
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7424688 |
Designing and fabrication of a semiconductor device
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface...
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7424689 |
Gated clock conversion
Gated clock signals in ASIC designs are automatically optimized for implementation with a programmable device. Components having gated clock signals are identified and converted to operate directly...
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7424418 |
Method for simulation with optimized kernels and debugging with unoptimized kernels
A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the...
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