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6988251 |
Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs
A semiconductor device comprising one or more diffused memories and one or more diffused regions. The one or more diffused regions may be configured to provide one or more ports for the one or more...
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6988256 |
Method and apparatus for pre-computing and using multiple placement cost attributes to quantify the quality of a placement configuration within a partitioned region
One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC...
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6986109 |
Practical method for hierarchical-preserving layout optimization of integrated circuit layout
The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these...
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6986118 |
Method for controlling semiconductor chips and control apparatus
The invention relates to a method for operating semiconductor chips, particularly memory chips, which are arranged in groups on modules which are connected to a common data bus wherein each...
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6986119 |
Method of forming tree structure type circuit, and computer product
A method of forming a tree structure type circuit includes the steps of dividing a division target region of LSI into a plurality of regions, placing constituent elements as distribution targets in...
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6986116 |
Signal balancing between voltage domains
A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using...
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6983235 |
Method and apparatus for implementing constant latency Z-domain transfer functions using processor elements of variable latency
In an illustrative embodiment, a desired signal processing transfer function is implemented using a generic pipelined data processor having variable latency followed by a variable latency...
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6983430 |
Method of resolving mismatched parameters in computer-aided integrated circuit design
A system and method for resolving mismatched parameters in computer-aided design of integrated circuits during schematic migration. The system compares the parameters within the circuit primitives...
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6983429 |
Formal proof methods for analyzing circuit loading problems under operating conditions
A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a...
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6983431 |
Simultaneous placement of large and small cells in an electronic circuit
A method and system for the simultaneous placement of large and small cells in an electronic circuit. A coarse placement using well known methods may provide an initial placement of cells. Cells...
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6980941 |
Method and computer program product for realizing a system specification which is described in a system description language
A system design support system is disclosed, which handles specifications at system level, e.g., a specification of software executed by a computer, specification of hardware implemented by...
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6981231 |
System and method to reduce leakage power in an electronic device
A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a...
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6978431 |
Automatic placement and routing apparatus automatically inserting a capacitive cell
A redundancy detection unit refers to layout data stored in a data storage unit and reflecting completed automatic placement and routing to detect a redundant region in a region having a cell...
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6978425 |
Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners
A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating...
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6976232 |
Method of designing and making an integrated circuit
A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated...
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6973633 |
Caching of lithography and etch simulation results
One or more control points are identified within a reticle layout that is used in a simulation of a manufacturing process for an integrated device layer. Further, a current geometrical layout...
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6970814 |
Remote IP simulation modeling
A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit...
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6971074 |
Layout device
A layout device includes a processing type setting part for classifying a layout of a semiconductor integrated circuit in every area in accordance with the percentage voltage drop in the circuit,...
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6971080 |
Placement based design cells injection into an integrated circuit design
An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a...
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6971079 |
Accuracy of timing analysis using region-based voltage drop budgets
A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an...
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6968517 |
Method of interactive optimization in circuit design
A method of interactively determining at least one optimized design candidate using an optimizer, the optimizer having a generation algorithm and an objective function, the optimized design...
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6968306 |
Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three...
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6968519 |
System and method for using IDDQ pattern generation for burn-in tests
A method and system are disclosed for efficiently and effectively toggling logic states of chip elements during a burn-in process of a digital integrated circuit chip. A set of IDDQ patterns are...
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6968524 |
Method and apparatus to optimize an integrated circuit design using transistor folding
A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout...
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6968518 |
Method of resolving missing graphical symbols in computer-aided integrated circuit design
A system and method is presented for resolving missing graphical symbols in computer-aided design of integrated circuits during schematic migration. The system inserts a substitute target graphical...
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6966045 |
Method and computer program product for estimating wire loads
A wire load estimating method comprises (1) reading a netlist; (2) generating connection information including the names of signals, the identification names and the names of pins of instances...
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6966041 |
Chip fabrication procedure and simulation method for chip testing with performance pre-testing
The present invention discloses a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing. The chip fabrication procedure with performance...
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6966043 |
Method for designing minimal cost, timing correct hardware during circuit synthesis
A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from...
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6964026 |
Method of updating a semiconductor design
A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions,...
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6964027 |
System and method for optimizing exceptions
A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new...
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6961918 |
System for intellectual property reuse in integrated circuit design
The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment. The system allows administrators to define standardized component...
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6961916 |
Placement method for integrated circuit design using topo-clustering
The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered...
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6958654 |
Layout technique for matched resistors on an integrated circuit substrate
Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of...
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6957402 |
Yield maximization in the manufacture of integrated circuits
A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard...
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6957412 |
Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements
Techniques are provided that combine functional blocks in a user design into fewer programmable circuit elements. Systems and methods of the present invention can combine functional blocks in a...
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6957404 |
Model checking with layered localization reduction
A method for verifying a property of a complete model of a system under study includes abstracting at least some of the variables from the model so as to produce an abstract model of the system....
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6957410 |
Method and apparatus for adaptively selecting the wiring model for a design region
Some embodiments provide a method of routing nets in a region of an integrated-circuit layout. This method initially identifies a characteristic of the region, and then selects a wiring model from...
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6957400 |
Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design
To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is...
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6954917 |
Function block architecture for gate array and method for forming an asic
A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place...
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6954914 |
Method and apparatus for signal electromigration analysis
The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global...
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6954921 |
Method and apparatus for automatic analog/mixed signal system design using geometric programming
A method is described that involves recognizing that a variable within a monomial or posynomial expression for a characteristic of an analog or mixed signal system has a dependency on a lower level...
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6952816 |
Methods and apparatus for digital circuit design generation
A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for...
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6950997 |
Method and system for low noise integrated circuit design
A method for designing an integrated circuit by a user, including: evaluating noise parameters for design elements of an integrated circuit design; determining if the noise parameters meet noise...
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6950996 |
Interconnect delay and slew metrics based on the lognormal distribution
A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a...
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6950998 |
Place-and-route with power analysis
Method and apparatus for placing and routing an electronic circuit design. Various embodiments are disclosed for analyzing placed and/or routed designs for power consumption characteristics and...
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6948139 |
Method for combining states
A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of...
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6948145 |
Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements
A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool...
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6948144 |
Method and apparatus for costing a path expansion
Some embodiments of the invention provide a method of propagating a first cost function that is defined over a first state to a second slate in a space representing a design-layout region. In some...
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6948138 |
Method for positioning I/O buffers and pads in an IC layout
A method for use by a placement and routing tool automatically selects positions for all n I/O buffers of an IC from among a set of m available legal positions for such buffers within an IC layout...
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6944844 |
System and method to determine impact of line end shortening
A critical dimension, or width, of a feature, or a semiconductor device, can be measured to provide direct and meaningful information regarding the impact of line end shortening, or length, on the...
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