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7036109 |
Imaging integrated circuits with focused ion beam
Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of...
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7036104 |
Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes
A method of and system for optimizing a tree to meet timing constraints inserts buffers at selected ones of the internal nodes of a tree to form a plurality of subtrees. The method sizes the wires...
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7036106 |
Automated processor generation system for designing a configurable processor and method for the same
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions...
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7032194 |
Layout correction algorithms for removing stress and other physical effect induced process deviation
A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the...
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7032191 |
Method and architecture for integrated circuit design and manufacture
A system for integrated circuit (IC) design. A structural multi-project wafer (SMPW) comprises a plurality of pre-manufactured and pre-validated functional blocks. The SMPW is pre-fabricated up to...
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7032195 |
Noise suppression component selecting method and program
In a method of selecting a suitable noise suppression component, an input signal to a digital circuit including a transmitter IC, a noise suppression filter, a transmission line, and a receiver IC...
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7032202 |
System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains
A method and system are disclosed for balancing a plurality of flip-flops across a number of global scan chains in a design of a digital integrated circuit chip. The design of the chip is organized...
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7028272 |
Reducing cell library development cycle time
An integrated tool which allows layouts for cells to be generated using a combination of synthesis, migration and manual approaches. In an embodiment, a compaction tool of a migration engine/module...
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7028280 |
IC layout buffer insertion method
An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the...
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7028273 |
Delay optimization designing system and delay optimization designing method for a logic circuit and control program
A delay optimization designing system and method is disclosed by which reduction of outputting delay and setup time of flip-flops and clock skew can be achieved and sufficient delay optimization...
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7024638 |
Method for creating patterns for producing integrated circuits
To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less...
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7024636 |
Chip management system
A method and system for automatically guiding a user through a design flow for an integrated circuit are disclosed. The method and system include displaying a design flow user interface on a user's...
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7024640 |
Integrated circuit cell identification
Apparatus, method and program product for evaluating design code of an integrated circuit. A program assigns an identifier to a cell based upon a cell characteristic. The program catalogs the...
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7020857 |
Method and apparatus for providing noise suppression in a integrated circuit
A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are...
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7020865 |
Process for designing comparators and adders of small depth
Logic circuits for logical operations, based on a function f N =x 1 OR (x 2 AND (x 3 OR (x 4 AND . . . x N . . . ))) or f′ N =x 1 AND (x 2 OR (x 3 AND (x 4 OR . . . x N . . . ))), are...
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7020855 |
Digital circuit layout techniques using identification of input equivalence
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the...
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7018746 |
Method of verifying the placement of sub-resolution assist features in a photomask layout
A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for...
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7020864 |
Optimized technology mapping techniques for programmable circuits
Technology mapping techniques are provided for converting a user design for a programmable integrated circuit to a network of programmable logic blocks. The technology mapping process attempts to...
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7016748 |
Collaborative integration of hybrid electronic and micro and sub-micro level aggregates
The present invention is directed to a system and method for providing a collaborative integration of hybrid electronic and micro and sub-micro, including nano, level aggregates. A method of...
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7017135 |
Method of designing semiconductor integrated circuit utilizing a scan test function
A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from...
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7017133 |
Designing a semiconductor device layout using polishing regions
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface...
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7017128 |
Concurrent electrical signal wiring optimization for an electronic package
The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring...
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7017130 |
Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits
A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI...
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7013437 |
High data rate differential signal line design for uniform characteristic impedance for high performance integrated circuit packages
Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto and the chip carrier has a signal...
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7013438 |
System chip synthesis
A technique to design deep sub-micron (DSM) integrated circuits is disclosed, in which global wire delays are minimized first, before performing logic synthesis. According to the present method, a...
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7013447 |
Method for converting a planar transistor design to a vertical double gate transistor design
A method for creating a vertical double-gate transistor design includes providing a planar transistor layout ( 10 ) having a gate layer ( 12 ) overlying an active layer ( 14 ). In one embodiment, a...
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7010765 |
Method for identifying removable inverters in an IC design
An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include...
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7010763 |
Method of optimizing and analyzing selected portions of a digital integrated circuit
Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit...
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7006962 |
Distributed delay prediction of multi-million gate deep sub-micron ASIC designs
A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic...
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7007258 |
Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout
A technique for generating via array is presented. An origin is set in one corner of a bounding box, and the bounding box is filled, according to at least one spacing rule, starting from the...
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7007247 |
Method and mechanism for RTL power optimization
The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a...
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7007248 |
Method and apparatus for implementing engineering change orders
A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active...
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7007259 |
Method for providing clock-net aware dummy metal using dummy regions
A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on...
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7003738 |
Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process
The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the...
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7003746 |
Method and apparatus for accelerating the verification of application specific integrated circuit designs
A method and system for accelerating software simulator operation with the aid of reprogrammable hardware such as Field Programmable Gate Array devices (FPGA). The method and system aid in...
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7003750 |
Topology based wire shielding generation
A topology based approach to shielding wire generation for an integrated circuit design. The present invention generates various templates by sizing one or more signal wire geometries. The various...
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7003743 |
Method and system of data processor design by sensitizing logical difference
A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test...
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7003739 |
Method and apparatus for finding optimal unification substitution for formulas in technology library
The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a...
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7003741 |
Method for determining load capacitance
A method for optimal driver selection uses a cost function that is based on the non-linear delay characteristics and the stage gain of the candidate drivers. The cost function operates to select an...
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6996787 |
Integrated circuit cells
According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a first logic path. The first transistor...
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6996786 |
Latch-up analysis and parameter modification
A latch-up analysis and parameter modification system, method and program product that analyzes a circuit design for latch-up sensitivity and allows for modifications of the circuit design to avoid...
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6996515 |
Enabling verification of a minimal level sensitive timing abstraction model
A method and a corresponding apparatus for verifying a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The method modifies and runs the...
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6993730 |
Method for rapidly determining the functional equivalence between two circuit models
This invention determines whether two circuit models have equivalent functionality. The method allows very fast comparison between two circuits taking advantage of previous work done. Whenever an...
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6993731 |
Optimization of digital designs
An application specific integrated circuit is optimized by translating a first representation of its digital design to a second representation. The second representation includes multiple syntactic...
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6990648 |
Method for identification of sub-optimally placed circuits
A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without...
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6990640 |
DIMM and method for producing a DIMM
A method for producing a DIMM having a reduced memory capacity. The method includes determining an amount by which a memory capacity of a DIMM can be reduced, and reducing the memory capacity of...
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6988251 |
Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs
A semiconductor device comprising one or more diffused memories and one or more diffused regions. The one or more diffused regions may be configured to provide one or more ports for the one or more...
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6988256 |
Method and apparatus for pre-computing and using multiple placement cost attributes to quantify the quality of a placement configuration within a partitioned region
One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC...
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6986109 |
Practical method for hierarchical-preserving layout optimization of integrated circuit layout
The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these...
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6986118 |
Method for controlling semiconductor chips and control apparatus
The invention relates to a method for operating semiconductor chips, particularly memory chips, which are arranged in groups on modules which are connected to a common data bus wherein each...
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