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7096451 |
Mesh plane generation and file storage
A method, system and program product implementing storage of a (power or ground) mesh plane file using a multiple line shape, possibly with the storage of lines also, to reduce file size. In...
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7096447 |
Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout
An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair...
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7093204 |
Method and apparatus for automated synthesis of multi-channel circuits
Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and...
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7093208 |
Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner...
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7093218 |
Incremental, assertion-based design verification
A design verification system includes a first verification engine to model the operation of a first design of an integrated circuit to obtain verification results including the model's adherence to...
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7093220 |
Method for generating constrained component placement for integrated circuits and packages
A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a...
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7093217 |
Method and apparatus for determining the optimal fanout across a logic element
A method of determining an optimal transistor fanout. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that...
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7089519 |
Method and system for performing placement on non Manhattan semiconductor integrated circuits
The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an...
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7089524 |
Topological vias route wherein the topological via does not have a coordinate within the region
Some embodiments of the invention provide a method for generating multi-layer topological routes in a region of a design layout. The method selects a net that has routable elements on a several...
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7089521 |
Method for legalizing the placement of cells in an integrated circuit layout
A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts...
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7089525 |
Semiconductor device and method for fabricating the same
The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated...
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7089512 |
Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits
A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices;...
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7089510 |
Method and program product of level converter optimization
A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and...
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7084464 |
Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same
A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for...
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7086025 |
Programmable logic device partitioning method for application specific integrated circuit prototyping
The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by...
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7086027 |
Method and apparatus for constraint graph based layout compaction for integrated circuits
A method of compacting a circuit layout includes determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit...
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7086015 |
Method of optimizing RTL code for multiplex structures
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an...
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7082582 |
Reducing clock skew in clock gating circuits
One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated...
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7080329 |
Method and apparatus for identifying optimized via locations
Some embodiments of the invention provide a method of identifying a via between at least two layers of a multi-layer design layout. The method identifies a region within which the via should be...
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7080343 |
Apparatus and method for selecting a printed circuit board
An apparatus and method for selecting an optimum printed circuit board in terms of its intended use before placement of components on the printed circuit board, information about components to be...
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7080337 |
Non-uniform decoupling capacitor distribution for providing more uniform noise reduction across chip
An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged...
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7076744 |
Circuit design method, apparatus, and program
A circuit design method able to design a processing circuit to be small in scale when designing a processing circuit for performing a plurality of different processings on predetermined data,...
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7076415 |
System for mixed signal synthesis
Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance...
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7076755 |
Method for successive placement based refinement of a generalized cost function
A generalized method for optimizing the global placement of a VLSI chip across multiple cost metrics, such as total wire length, timing, congestion, and signal integrity is described. The method...
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7076407 |
Space reduction in compositional state systems
Models in compositional state systems are reduced by defining a set of events of interest and defining a transitive effect machine for components in the model relative to the events of interest. A...
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7076405 |
Method for estimating power consumption and noise levels of an integrated circuit, and computer-readable recording medium storing a program for estimating power consumption and noise levels of an integrated circuit
The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of...
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7073156 |
Gate estimation process and method
A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design...
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7073145 |
Programmable delay method for hierarchical signal balancing
A method for signal balancing across multiple random logic macros. The method inserts a programmable delay element into the design before the last buffer level on all signal paths. The random logic...
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7069523 |
Automated selection and placement of memory during design of an integrated circuit
A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and...
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7069535 |
Optical proximity correction method using weighted priorities
A method of silicon design reproducibility enhancement using priority assignments prior to performing a conventional optical proximity correction process on a device. The present invention seeks to...
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7065728 |
Method for placing electrostatic discharge clamps within integrated circuit devices
A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible...
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7065721 |
Optimized bond out method for flip chip wafers
A method of optimizing a bond out design includes steps of: (a) receiving as input an initial bond out design including at least one selected I/O pad and a top redistribution layer; (b) determining...
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7065727 |
Optimal simultaneous design and floorplanning of integrated circuit
A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved...
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7065722 |
System and method for building a binary decision diagram associated with a target circuit
A method for constructing a binary decision diagram (BDD) is provided that includes constructing a first BDD data structure operable to reflect a function associated with a target circuit, the...
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7062725 |
Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit
A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is...
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7062727 |
Computer aided design systems and methods with reduced memory utilization
Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a...
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7058916 |
Method for automatically sizing and biasing circuits by means of a database
In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell...
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7058907 |
Reduction of cross-talk noise in VLSI circuits
A process for reducing cross-talk noise in a VLSI circuit is disclosed. The process identifies a victim net in an integrated circuit and calculates a change in ground capacitance for the victim net...
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7058912 |
Notifying status of execution of jobs used to characterize cells in an integrated circuit
The status of execution of jobs (used to characterize cells) is notified asynchronously. As a result, the processing and network resources may be optimally used. In an embodiment, a flow controller...
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7055115 |
Line width check in layout database
A method of performing a design rule check on an integrated circuit includes tagging at least one line in a schematic with a width marker and an associated width parameter, extracting the line...
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7055114 |
Systems and processes for asymmetrically shrinking a VLSI layout
Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is...
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7051313 |
Automatic generation of programmable logic device architectures
An “architecture generation engine” is operative with a CAD system to implement circuits into PLD (programmable logic device) architectures and to evaluate performances of different...
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7051295 |
IC design process including automated removal of body contacts from MOSFET devices
An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET...
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7051293 |
Method and apparatus for creating an extraction model
A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and...
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7051296 |
Method and apparatus for parallel carry chains
An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within...
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7047504 |
Method and program for designing semiconductor integrated circuits to optimize clock skews on plurality of clock paths
A method for designing semiconductor integrated circuits that efficiently optimizes clock skews in a plurality of clock modes in the case of designing semiconductor integrated circuits having a...
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7047139 |
Sharing information between instances of a propositional satisfiability (SAT) problem
A technique is disclosed for sharing information between closely-related SAT instances (instances with a non-empty intersection between their sets of clauses), which enables a speed-up in the...
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7047508 |
Method for performing multi-clock static timing analysis
A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be...
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7047505 |
Method for optimizing the characteristics of integrated circuits components from circuit specifications
A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator...
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7047506 |
Method to identify geometrically non-overlapping optimization partitions for parallel timing closure
A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths...
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