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7228503 |
Method for remote mask data jobview through a network
A method for remote mask data jobview through a network featuring 24-hour service, reduced cycle time and lower cost, whereby customers can obtain real time mask data access instead of downloading...
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7222327 |
Photo mask, method of manufacturing photo mask, and method of generating mask data
A photo mask includes a mask pattern formed by using a mask exposure pattern to exposure a mask substrate, the mask exposure pattern being formed by adding a proximity effect correction pattern to...
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7222326 |
Automatic process and design method, system and program product
A method, system and program product for generating a process aid on a wafer are disclosed. A “process aid” can be any device provided on a wafer that assists in some process step, but does not...
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7216314 |
Integrated circuit verification method
A method for verifying an integrated circuit comprising components connected by connections, the integrated circuit being defined by “physical” and “schematic” representations, comprising...
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7211369 |
VLSI-based system for durable high-density information storage
The invention relates to using VLSI techniques to store information on a substrate. One embodiment of a die with text deposited upon the die uses semiconductor processing techniques during...
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7213226 |
Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and software product for executing the correction method
A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern;...
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7207030 |
Method for improving a simulation model of photolithographic projection
A method is provided for improving a photolithographic simulation model of the photolithographic simulation of a pattern formed on a photomask. Proceeding from a two-dimensional simulation model...
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7207028 |
System for evaluating a design of a mask, exposure system, method for evaluating a design of a mask, method for manufacturing a semiconductor device and mask
A system for evaluating a design of a mask includes: an inspection data memory storing initial inspection data of an initial wafer fabricated by an initial mask; a design tool designing a modified...
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7203923 |
Capacitors integrated with inductive components
Techniques for producing integrated capacitors are disclosed. According to one of the techniques, one or more layers are introduced in conjunction with a ground layer supporting a substrate on...
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7203632 |
HDL co-simulation in a high-level modeling system
Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level...
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7200834 |
Exposure pattern forming method and exposure pattern
Disclosed is an exposure pattern forming method of forming an exposure pattern by correcting each pattern portion constituting a design pattern by a correction amount, which amount is previously...
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7197722 |
Optimization of sample plan for overlay
The present invention describes a method including: determining field-clustering scheme; selecting initial sample plan; establishing initial model of overlay, the initial model of overlay...
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7194709 |
Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies
A method, computer program product and system for assessing the impact of anomalies in a physical device. An anomaly may be detected in an integrated circuit. Upon detecting an anomaly, an image of...
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7194725 |
System and method for design rule creation and selection
A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures...
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7191428 |
Centerline-based pinch/bridge detection
A method for performing layout verification involves identifying feature centerlines in a mask layout, and then performing lithography simulation along the centerlines to generate a set of...
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7190455 |
Alignment method and apparatus and exposure apparatus
A method for detecting disposition of plurality of exposure shot areas of an object that is to be exposed includes a first detection step of detecting the alignment marks on the object, an...
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7188322 |
Circuit layout methodology using a shape processing application
A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology...
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7188162 |
Method and equipment for setting up a protocol/system protocol
A method is used for generating a system protocol for control and/or monitoring equipment for one or more machines and/or processes. The equipment comprises a number of modules which can...
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7185310 |
System and method for charge-balanced, continuous-write mask and wafer process for improved colinearity
A charge-balanced, continuous-write mask and wafer process changes the magneto resistive photo-definition step to a two-mask step operation. Critical images are written on one mask layer at a very...
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7185311 |
Mask evaluating method, mask evaluating system, method of manufacturing mask and computer program product
A photomask evaluating method comprises calculating a killer defect rate function with respect to a simulative defect pattern including a pattern of photomask and a plurality of defects, the killer...
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7185312 |
Exposure method for correcting line width variation in a photomask
A method for correcting line width variation occurring during a development process in fabricating a photomask and a recording medium in which the exposure method is recorded is provided, wherein...
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7181707 |
Method of setting process parameter and method of setting process parameter and/or design rule
Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to...
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7181722 |
Method of dividing circuit pattern, method of manufacturing stencil mask, stencil mask and method of exposure
A method of dividing a circuit pattern for creating complementary stencil masks corresponding to complementary patterns, the method comprising a step of dividing a circuit pattern into a plurality...
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7181721 |
Short edge management in rule based OPC
The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification...
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7175940 |
Method of two dimensional feature model calibration and optimization
A method for generating a photolithography mask for optically transferring a pattern formed in the mask onto a substrate utilizing an imaging system. The method includes the steps of: (a) defining...
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7175952 |
Method of generating mask distortion data, exposure method and method of producing semiconductor device
A method of generating mask distortion data capable of improving accuracy of distortion measurement, an exposure method using the same and a method of producing a semiconductor device, wherein a...
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7178128 |
Alternating phase shift mask design conflict resolution
Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other...
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7174531 |
Creating photolithographic masks
An embodiment of the present invention described and shown in the specification is a system for optimizing data used in creating a photolithographic mask. The system reads a definition of a layer...
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7174532 |
Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects
The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an...
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7171645 |
Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device
To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high. A method of generating a pattern for a...
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7169515 |
Phase conflict resolution for photolithographic masks
A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase...
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7171637 |
Translation generation for a mask pattern
Generation of one or more translations is described. The generated translations may be applied to a mask pattern so that the pattern may be moved to cover one or more mask defects in part or in...
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7167768 |
Board work system having provision for establishing operating environment suitable for operator, and process of establishing the suitable operating environment
A board work system operable by a plurality of operators assigned in turn to operate. The system includes (a) at least one device changeable to each one of a plurality of different modes; (b) a...
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7165233 |
Test ket layout for precisely monitoring 3-foil lens aberration effects
An H-shaped test key layout for exclusively monitoring 3-foil lens aberration effects during the fabrication of deep-trench capacitor memory devices is disclosed. The COMA lens aberration effect...
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7159205 |
Use of non-lithographic shrink techniques for fabrication/making of imprints masks
The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the...
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7159197 |
Shape-based geometry engine to perform smoothing and other layout beautification operations
A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified...
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7155699 |
Streamlined IC mask layout optical and process correction through correction reuse
An EDA tool is provided with an OPC module that performs optical and/or process pre-compensations on an IC mask layout in a streamlined manner, reusing determined corrections for a first area on a...
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7155689 |
Design-manufacturing interface via a unified model
Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have...
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7155698 |
Method of locating areas in an image such as a photo mask layout that are sensitive to residual processing effects
Images such as mask layouts, signatures, and photographs are compared to identify similarities or dissimilarities in the images. Descriptions of the images use geometric shapes including lines,...
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7152219 |
Reference image generation from subject image for photolithography mask analysis
A reference image is generated from a subject image of at least a portion of a photolithography mask to enable a photolithography mask inspection and analysis system that otherwise cannot generate...
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7147976 |
Binary OPC for assist feature layout optimization
A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of...
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7149998 |
Lithography process modeling of asymmetric patterns
A lithography process model is generated to account for asymmetric printing of a feature of a target pattern to help better predict how the target pattern will print. The process model for one...
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7149999 |
Method for correcting a mask design layout
A method for performing a mask design layout resolution enhancement includes determining a level of correction for a mask design layout for a predetermined parametric yield with a minimum total...
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7146599 |
Method for using asymmetric OPC structures on line ends of semiconductor pattern layers
A method is disclosed for conducting optical proximity correction (OPC) on at least two features in a circuit design. After detecting a first feature having at least one end thereof to be in the...
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7146597 |
CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for executing the CAD method
A design method encompasses: determining a direction of a subject wiring level in a multi-level interconnection of semiconductor integrated circuit as a subject-level priority direction; designing...
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7143329 |
FPGA configuration memory with built-in error correction mechanism
A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory...
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7143389 |
Systems and methods for generating node level bypass capacitor models
Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated...
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7139997 |
Method and system for checking operation of a mask generation algorithm
Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol...
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7139996 |
Mask pattern correction apparatus and mask pattern correction method and mask preparation method and method of production of a semiconductor device
By correcting an optical proximity effect with respect to design patterns by an optical proximity effect correcting means and simulating patterns after the correction of optical proximity effect by...
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7139998 |
Photomask designing method, pattern predicting method and computer program product
A photomask designing method used in a lithography process, the lithography process comprises illuminating light on a photomask and converging the light which has passed through the photomask on a...
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