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7620942 |
Method and system for parameterization of imperative-language functions intended as hardware generators
A method ( 100 ) of translating an imperative language function into a parameterized hardware component can include the steps of using ( 102 ) formal imperative function arguments to represent at...
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7620929 |
Programmable logic device having a programmable selector circuit
A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector...
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7620928 |
Method and apparatus for synthesizing a hardware system from a software description
A method and an apparatus take software source code to synthesize a hardware platform for running the software. The method determines which processor is suitable for running the code and meeting...
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7620927 |
Method and apparatus for circuit design closure using partitions
A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input...
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7620926 |
Methods and structures for flexible power management in integrated circuits
Structures and methods of efficiently implementing power management in integrated circuits (ICs). An IC includes columns of logic blocks and columns of power management blocks (PMBs). The columns...
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7620925 |
Method and apparatus for performing post-placement routability optimization
A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after...
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7620924 |
Base platforms with combined ASIC and FPGA features and process of using the same
A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to...
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7620922 |
Method and system for optimized circuit autorouting
An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit...
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7620917 |
Methods and apparatuses for automated circuit design
Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through...
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7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective...
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7617472 |
Regional signal-distribution network for an integrated circuit
Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The...
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7617471 |
Processor event interface for programmable integrated circuit based circuit designs
A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A...
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7614029 |
Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric
Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and...
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7613599 |
Method and system for virtual prototyping
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are...
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7610573 |
Implementation of alternate solutions in technology mapping and placement
A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of...
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7610571 |
Method and system for simulating state retention of an RTL design
Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL)...
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7610569 |
Chip design verification apparatus and data communication method for the same
A method of verifying a chip design includes: a software side operation step of transmitting output data generated by an operation of a software block to an interface unit, determining whether...
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7603647 |
Recognition of a state machine in high-level integrated circuit description language code
A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as...
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7603646 |
Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables
Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for...
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7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry
Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first...
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7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method
An assertion generating system is disclosed. In an assertion generating system 207 , a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7596772 |
Methodology and system for setup/hold time characterization of analog IP
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The...
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7596769 |
Simulation of power domain isolation
Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL)...
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RE40925 |
Methods for automatically pipelining loops
A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level...
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7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been...
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7594200 |
Method for finding multi-cycle clock gating
An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The...
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7590965 |
Methods of generating a design architecture tailored to specified requirements of a PLD design
Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design...
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7590964 |
Method and system for automatic generation of processor datapaths using instruction set architecture implementing means
Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for...
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7587698 |
Operational time extension
Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The...
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7587697 |
System and method of mapping memory blocks in a configurable integrated circuit
Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions...
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7587688 |
User-directed timing-driven synthesis
Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori...
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7584460 |
Process and apparatus for abstracting IC design files
File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to...
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7584449 |
Logic synthesis of multi-level domino asynchronous pipelines
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a...
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7584448 |
Constructing a model of a programmable logic device
A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of...
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7584437 |
Assuring correct data entry to generate shells for a semiconductor platform
A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated...
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7581201 |
System and method for sign-off timing closure of a VLSI chip
A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in...
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7576569 |
Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit
A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life...
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7574688 |
Using high-level language functions in HDL synthesis tools
A method of integrating a High-level Language (HLL) function with a Hardware Description Language (HDL) representation of a circuit design can include identifying an attribute of the HDL...
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7571422 |
Method for generating a design rule map having spatially varying overlay budget
The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if...
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7571416 |
Automatic design device, method, and program for semiconductor integrated circuits
An automatic design device includes: a calculating section calculating additional geometries added to basic geometries including wiring lines and vias arranged on a chip region; a classifying...
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7571414 |
Multi-project system-on-chip and its method
A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral...
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7571404 |
Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise
A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network...
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7571396 |
System and method for providing swap path voltage and temperature compensation
The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes...
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7568178 |
System simulation and graphical data flow programming in a common environment using wire data flow
Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various...
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7568173 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration
Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in...
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7565638 |
Density-based layer filler for integrated circuit design
A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may...
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7565632 |
Behavioral synthesizer system, operation synthesizing method and program
A behavioral synthesis system which synthesizes behavior without inline expansion of a callee function, even one which has a pointer as an argument during the synthesis of a caller function. There...
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7562322 |
Design verification for a switching network logic using formal techniques
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the...
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7562321 |
Method and apparatus for structured ASIC test point insertion
Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the...
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