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7437693 |
Method and system for s-parameter generation
Disclosed are methods and systems for generating S-parameters. In some embodiments, the methods and systems comprise creating (e.g., extracting, calculating, generating), in part or whole into the...
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7437692 |
Memory debugger for system-on-a-chip designs
A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated...
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7434181 |
Debugger of an electronic circuit manufactured based on a program in hardware description language
A device for debugging an electronic circuit manufactured based on an initial program in hardware description language comprising an instrumentation unit capable of determining a first additional...
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7434193 |
Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights
In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible...
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7434192 |
Techniques for optimizing design of a hard intellectual property block for data transmission
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be...
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7430726 |
System for delay reduction during technology mapping in FPGA
The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel...
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7430727 |
Hardware component graph to hardware description language translation method
An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component...
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7430725 |
Suite of tools to design integrated circuits
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification...
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7428721 |
Operational cycle assignment in a configurable IC
Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for...
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7426707 |
Layout design method for semiconductor integrated circuit, and semiconductor integrated circuit
In a layout design method for a semiconductor integrated circuit, a cell layout library is provided which stores structure information of functional cells and a plurality of groups of filler cells,...
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7426461 |
Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities
In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities...
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7426668 |
Performing memory built-in-self-test (MBIST)
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more...
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7426709 |
Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system
An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to...
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7424689 |
Gated clock conversion
Gated clock signals in ASIC designs are automatically optimized for implementation with a programmable device. Components having gated clock signals are identified and converted to operate directly...
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7424418 |
Method for simulation with optimized kernels and debugging with unoptimized kernels
A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the...
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7424655 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective...
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7418683 |
Constraint assistant for circuit design
A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types...
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7418675 |
System and method for reducing the power consumption of clock systems
A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells...
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7415691 |
Method and system for outputting a sequence of commands and data described by a flowchart
The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a...
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7415692 |
Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
A programming method efficiently programs programmable logic devices of the type having specialized multiplier blocks that include multipliers and other arithmetic function elements. Such blocks...
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7415693 |
Method and apparatus for reducing synthesis runtime
A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second...
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7415689 |
Automatic configuration of a microprocessor influenced by an input program
An automatic process for configuring a microprocessor architecture that consists of a number of execution units with configurable connectivity between them. The data and control flows within an...
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7412680 |
Method and apparatus for performing integrated global routing and buffer insertion
A method for designing a system on an integrated circuit includes synthesizing the system. The system is placed on the integrated circuit. Buffer insertion is performed while selecting new branch...
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7412684 |
Loop manipulation in a behavioral synthesis tool
Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another...
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7412668 |
Integrated system noise management—decoupling capacitance
A method for noise suppression for a system implementation of an integrated circuit design is described. First clock operating parameters for logic blocks of the integrated circuit design are...
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7409650 |
Low power consumption designing method of semiconductor integrated circuit
In a standard cell synthesizing step 101 , a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance...
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7409658 |
Methods and systems for mixed-mode physical synthesis in electronic design automation
Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections...
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7409656 |
Method and system for parallelizing computing operations
Disclosed is an improved method and system for implementing parallel processing of computing operations by effectively handling dependencies between different sequences of computing operations. In...
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7409670 |
Scheduling logic on a programmable device implemented using a high-level language
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written...
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7406673 |
Method and system for identifying essential configuration bits
A method and system are disclosed. The method and system provide the ability to identify a configuration bit as an essential configuration bit. The identifying that is performed uses a...
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7406672 |
Method and apparatus for constructing and optimizing a skew of a clock tree
An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs,...
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7406669 |
Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models
A method of enabling CRPR in an ETM. In an exemplary embodiment, the method includes locating a plurality of clocks defined within a core. The method may also include determining if one of the...
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7406668 |
Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations
Implementation of a logic design in either an FPGA or a structured ASIC is facilitated by designing either type of implementation so that it takes into account the possible need to migrate the...
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7404174 |
method for generating a set of test patterns for an optical proximity correction algorithm
A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices;...
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7404168 |
Detailed placer for optimizing high density cell placement in a linear runtime
A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to...
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7404160 |
Method and system for hardware based reporting of assertion information for emulation and hardware acceleration
A method and system for hardware based reporting of assertion information for emulation and hardware acceleration is disclosed. In one embodiment, a method of performing assertion-based...
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7404172 |
Method for the synthesis of VLSI systems based on data-driven decomposition
The present invention is a systematic and data-driven-decomposition (DDD) method and apparatus for use in VLSI synthesis. The invention decomposes a high level program circuit description into a...
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7401314 |
Method and apparatus for performing compound duplication of components on field programmable gate arrays
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes duplicating a plurality of components in response to slack values associated with...
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7401313 |
Method and apparatus for controlling congestion during integrated circuit design resynthesis
The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing...
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7401319 |
Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design
A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational...
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7398505 |
Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout
An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit...
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7398497 |
Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method
An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general...
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7398507 |
Method of automatic synthesis of sequential quantum Boolean circuits
A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum...
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7398503 |
Method and apparatus for pre-tabulating sub-networks
A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network based on the...
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7398506 |
Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing
A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to...
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7398496 |
Unified placer infrastructure
Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer...
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7398504 |
Program, method and apparatus for analyzing transmission signals
From design information on a circuit board a wiring designation unit designates a wiring model for signal analysis. A first analysis unit generates, through a 3-D electromagnetic analysis, a first...
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7398488 |
Trace equivalence identification through structural isomorphism detection with on the fly logic writing
A method for performing trace equivalent identification by structural isomorphism detection, the method comprising: synthesizing a first netlist into a second netlist, the second netlist including...
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7395521 |
Method and apparatus for translating an imperative programming language description of a circuit into a hardware description
Method and apparatus for translating an imperative programming language description of a circuit into a hardware description is described. In one example, a state object in a function of the...
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7392498 |
Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device
Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (...
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