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7478346 |
Debugging system for gate level IC designs
A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump...
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7478350 |
Model modification method for timing Interoperability for simulating hardware
Integrated circuit design often involves combination of blocks of circuit from different sources to create new designs. However, a simulation of a block developed using a given method may not be...
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7478351 |
Designing system and method for designing a system LSI
A method for designing a system LSI includes the steps of dividing an algorithmic description (D 1 ) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior...
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7475370 |
System for verification using reachability overapproximation
A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design,...
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7475377 |
Semiconductor device design system and method, and software product for the same
A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a...
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7475369 |
Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification
Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the...
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7472359 |
Behavioral transformations for hardware synthesis and code optimization based on Taylor Expansion Diagrams
A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated...
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7472371 |
Description style conversion method, program, and system of logic circuit
A logic circuit described in the netlist style HDL and a lower-level logic circuit (lower-level module) of a library which corresponds to an instance in the logic circuit and is described in the...
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7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
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7472369 |
Embedding identification information on programmable devices
Methods and apparatus are provided for embedding identification information on a programmable chip. Parameterizable components are selected for implementation on a programmable chip. Information...
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7472358 |
Method and system for outputting a sequence of commands and data described by a flowchart
The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of...
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7472361 |
System and method for generating a plurality of models at different levels of abstraction from a single master model
A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that...
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7469394 |
Timing variation aware compilation
Design compilation software uses statistical analysis techniques to account for variations in device attributes. A compilation phase determines statistical attributes of edges and other elements of...
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7469399 |
Semi-flattened pin optimization process for hierarchical physical designs
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of...
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7469390 |
Method and software tool for automatic generation of software for integrated circuit processors
A method of generating software code for a processor of an IC based on a simple input description of the IC's standards. The method includes generating a macros description of each of the...
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7467361 |
Pipeline high-level synthesis system and method
According to one embodiment, a pipeline high-level synthesis system receives a high-level description and performs pipeline high-level synthesis for its loop description part to generate a...
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7467362 |
Failure detection improvement apparatus, failure detection improvement program, failure detection improvement method
A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to...
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7464360 |
Common interface framework for developing field programmable device based applications independent of a target circuit board
A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD)....
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7464361 |
System and method for asynchronous logic synthesis from high-level synchronous descriptions
A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior.
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7464350 |
Method of and circuit for verifying a layout of an integrated circuit device
A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated...
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7464362 |
Method and apparatus for performing incremental compilation
A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second...
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7464348 |
Method and system for mapping source elements to destination elements as interconnect routing assignments
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for...
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7464345 |
Resource estimation for design planning
A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the...
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7464353 |
Method and apparatus for generating technology independent delays
A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication...
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7464363 |
Verification support device, verification support method, and computer product
A verification support device supports logic verification of a design object corresponding to modified sequence diagrams obtained by modifying sequence diagrams expressing processes of a design...
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7461360 |
Validating very large network simulation results
A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws...
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7461359 |
Method and mechanism for determining shape connectivity
A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of...
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7454738 |
Synthesis approach for active leakage power reduction using dynamic supply gating
A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A...
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7454732 |
Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs
Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a...
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7454722 |
Acyclic modeling of combinational loops
Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where...
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7454737 |
Method, system and program product for specifying and using register entities to configure a simulated or physical digital system
In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and...
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7451427 |
Bus representation for efficient physical synthesis of integrated circuit designs
A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the...
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7451425 |
Determining controlling pins for a tile module of a programmable logic device
A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile...
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7451423 |
Determining indices of configuration memory cell modules of a programmable logic device
A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A...
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7451426 |
Application specific configurable logic IP
An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level...
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7448009 |
Method of leakage optimization in integrated circuit design
This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells,...
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7448006 |
Logic-synthesis method and logic synthesizer
The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes...
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7448002 |
Inspection system
An inspection system applicable to a data processing device installed with a PCB (printed circuit board) design software and a display unit is proposed, wherein the PCB design software is used for...
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7448007 |
Slew constrained minimum cost buffering
A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a...
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7444601 |
Trusted computing platform
In a computing platform, a trusted hardware device ( 24 ) is added to the motherboard ( 20 ). The trusted hardware device ( 24 ) is configured to acquire an integrity metric, for example a hash of...
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7444574 |
Stimulus extraction and sequence generation for an electric device under test
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from...
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7444605 |
Generating a base curve database to reduce storage cost
An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing...
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7444613 |
Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This...
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7441210 |
On-the-fly RTL instructor for advanced DFT and design closure
A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the...
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7441212 |
State machine recognition and optimization
State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each...
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7441225 |
Method and device for synthesising an electrical architecture
A method of synthesizing an electrical or electronic architecture of at least one part of a product including electrical wires and electrical and electronic components, such as sensors, actuators,...
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7441208 |
Methods for designing integrated circuits
The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process....
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7441209 |
Method, system and program product for providing a configuration specification language supporting error checking dials
A digital system includes one or more design entities containing a functional portion of the digital system. Within a configuration database, one or more configuration entities are instantiated....
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7437700 |
Automated processor generation system and method for designing a configurable processor
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions...
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7437701 |
Simulation of a programming language specification of a circuit design
Various approaches for simulating a circuit design are disclosed. In one approach, a first specification of a testbench and a second specification of the circuit design are generated in a hardware...
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