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6968515 |
Semiconductor circuit designing apparatus and a semiconductor circuit designing method in which the number of steps in a circuit design and a layout design is reduced
A semiconductor circuit designing apparatus includes a circuit design unit executing and an inspection item database section. The circuit design unit executes a logical design of a semiconductor...
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6968523 |
Design method of logic circuit using data flow graph
An algorithm of a logic circuit is converted from an operation description having operators into a data flow graph having operation nodes executing the operators arranged in order of the executing....
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6967348 |
Signal sharing circuit with microelectric die isolation features
A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively...
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6966045 |
Method and computer program product for estimating wire loads
A wire load estimating method comprises (1) reading a netlist; (2) generating connection information including the names of signals, the identification names and the names of pins of instances...
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6966046 |
CMOS tapered gate and synthesis method
A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate...
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6961919 |
Method of designing integrated circuit having both configurable and fixed logic circuitry
A method for designing an integrated circuit having both fixed logic and programmable logic components. An intended set of applications for the integrated circuit is first identified. In addition,...
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6961918 |
System for intellectual property reuse in integrated circuit design
The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment. The system allows administrators to define standardized component...
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6959428 |
Designing and testing the interconnection of addressable devices of integrated circuits
A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool...
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6957413 |
System and method for specifying integrated circuit probe locations
A method for including probe locations in an integrated circuit may include specifying probe cells prior to the place and route stage of the design process. The probe cell locations may be...
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6957400 |
Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design
To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is...
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6954917 |
Function block architecture for gate array and method for forming an asic
A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place...
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6954921 |
Method and apparatus for automatic analog/mixed signal system design using geometric programming
A method is described that involves recognizing that a variable within a monomial or posynomial expression for a characteristic of an analog or mixed signal system has a dependency on a lower level...
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6952817 |
Generating hardware interfaces for designs specified in a high level language
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to...
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6952816 |
Methods and apparatus for digital circuit design generation
A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for...
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6952810 |
Coding speed and correctness of hardware description language (HDL) descriptions of hardware
A method is provided, the method comprising collecting related signals capable of having unrelated names into a Krutibus, defining a bus capable of connecting the related signals in a bus...
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6948145 |
Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements
A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool...
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6948141 |
Apparatus and methods for determining critical area of semiconductor design data
Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The...
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6948148 |
System for automated generation of data path macro cells
Generating a data path macro cell based upon a text format template comprising variables. The system provides for creating a text format template by generating a text format representation of a...
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6944834 |
Method and apparatus for modeling dynamic systems
A method and system are disclosed for generating descriptions of circuits representative of the behavior of dynamic systems. A state space model representing a dynamic system may be used to...
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6941533 |
Clock tree synthesis with skew for memory devices
A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells,...
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6941257 |
Hierarchical processing of simulation model events
A method, system, and data structure for instrumenting a cross-hierarchical simulation event are disclosed herein. The cross-hierarchical simulation event is a function of a first simulation event...
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6941541 |
Efficient pipelining of synthesized synchronous circuits
Method and apparatus for generating a pipelined synchronized circuit representation of a program loop. A dependence graph is generated from the program loop. The dependence graph represents...
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6941539 |
Efficiency of reconfigurable hardware
The present invention includes a method of computing a function array in reconfigurable hardware that includes forming in the reconfigurable hardware a first delay queue and a second delay queue,...
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6941527 |
Method, system and program product for reducing a size of a configuration database utilized to configure a hardware digital system
A method of constructing a compact configuration database is disclosed. The configuration database originally includes a plurality of Dial instance data structures each corresponding to a...
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6937973 |
Design of an application specific processor (ASP)
A method of operating a computer system to design an application specific processor (ASP) comprises defining a set of peripherals for the ASP which are responsive to stimuli and which communicate...
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6938237 |
Method, apparatus, and system for hardware design and synthesis
According to one embodiment of the present invention, a method and system for VLSI hardware design and synthesis is provided in which components provided by a heterogeneous modeling framework are...
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6934927 |
Turn architecture for routing resources in a field programmable gate array
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery....
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6931617 |
Mask cost driven logic optimization and synthesis
The cost of making a mask set cost has been dramatically increasing due to demand for very small device sizes as well as higher chip complexity. Thus, users would like to minimize the total mask...
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6925406 |
Scan test viewing and analysis tool
A scan test viewing and analysis tool for an integrated circuit tester provides inter-related views of scan tests on an integrated circuit device. The tool processes a test program specification,...
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6925628 |
High-level synthesis method
A high-level synthesis method of the present invention includes: generating a CDFG (Control Data Flow Graph) based an input file describing a behavior of a digital circuit; allocating each node of...
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6925616 |
Method to test power distribution system
A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of...
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6922818 |
Method of power consumption reduction in clocked circuits
A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more...
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6918103 |
Integrated circuit configuration
An integrated circuit containing a plurality of data processing circuit elements 4, 6, 8, 10, 12, 14 and 16 is provided with a configuration data memory 12 . Upon initialisation of the...
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6918098 |
Random code generation using genetic algorithms
Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability...
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6915252 |
Method and system for ensuring consistency of design rule application in a CAD environment
In a computer-aided design environment, a method for ensuring consistency of design rule application among a plurality of CAD tool programs contemplates the use of a global design rule definition...
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6912601 |
Method of programming PLDs using a wireless link
An apparatus comprising a wireless transceiver and a programmable logic circuit. The wireless transceiver may be coupled to the programmable logic circuit. The programmable logic circuit may...
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6910202 |
Logic synthesis device and logic synthesis method
An analysis part analyzes a description of a logic design; an extraction part extracts a part of the description of the logic design having a fan-out number beyond a predetermined value, based on...
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6907588 |
Congestion estimation for register transfer level code
A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor...
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6907599 |
Synthesis of verification languages
A method for synthesizing a verification language, and thereby enabling the verification language to be compiled into a target language. This method enables the underlying control structure of the...
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6907595 |
Partial reconfiguration of a programmable logic device using an on-chip processor
A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration...
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6901572 |
Power sequence controller programming technique
A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user...
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6901568 |
Method for fabricating transistor
Disclosed is a method for correcting a transistor of a predetermined threshold value. According to the method, after preparing a gate 13 of the transistor, depending on how well the gate is...
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6898767 |
Method and apparatus for custom design in a standard cell design environment
Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be...
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6895565 |
Methods for predicting board test coverage
Disclosed are methods for predicting board test coverage. In one method, board test coverage is predicted by enumerating potentially defective properties for a board design; determining how each of...
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6895524 |
Circuit reduction technique for improving clock net analysis performance
A method for reducing a transistor circuit netlist for clock network timing verification is provided. Further, a simulation tool that reduces a transistor circuit netlist such that nonlinear...
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6892373 |
Integrated circuit cell library
According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the...
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6889366 |
System and method for coevolutionary circuit design
The present invention is directed to a system and method for coevolutionary circuit design. A system suitable for providing integrated circuit design may include a memory suitable for storing a...
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6889180 |
Method and apparatus for a monitor that detects and reports a status event to a database
The present invention is a monitor that detects a design verification event and reports a status event to a database. One embodiment of the present invention comprises a monitor declaration, zero...
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6889368 |
Method and apparatus for localizing faults within a programmable logic device
Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to...
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6886122 |
Method for testing integrated circuits with memory element access
A method for testing an integrated circuit having memory elements which are written and/or read via an access path to the memory elements from a terminal external to the circuit. A boundary scan...
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