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7131077 |
Using an embedded processor to implement a finite state machine
Method and System for implementing a Finite State Machine (FSM) using software executed on a processor and having accurate timing information is described, where the accurate timing information is...
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7131080 |
Simulation management system
A method, apparatus and program product oversee and coordinate the automatic generation, monitoring and submission of package files and other modeling processes to enable focused, flexible and...
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7131099 |
Method, apparatus, and computer program product for RTL power sequencing simulation of voltage islands
A method, apparatus and computer program product are provided for implementing RTL power sequencing simulation of voltage islands for application specific integrated circuit (ASIC) designs. RTL...
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7131086 |
Logic verification device, logic verification method and logic verification computer program
A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the...
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7127686 |
Method for validating simulation results of a system as well as equivalence comparison of digital circuits based on said method
The invention creates a technology for validating simulation results. The quickly growing number of components in modern complex systems often necessitates the introduction of abstractions, that...
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7127692 |
Timing abstraction and partitioning strategy
The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user...
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7124393 |
System and method for processing configuration information
A system, method and software product processes configuration information. One or more configuration elements are identified from one or more configuration commands and associated with design...
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7124392 |
Mapping of programmable logic devices
A method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Deviceoperates by selecting an unmapped or partially mapped LUT, and identifying a group of...
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7124391 |
Method and apparatus for dynamically connecting modules in a programmable logic device
Method and apparatus for dynamically connecting modules within a programmable logic device is described. In an example, a programmable logic device is programmed with modular circuits. A bitstream...
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7124377 |
Design method for essentially digital systems and components thereof and essentially digital systems made in accordance with the method
The present invention relates to the design of essentially digital systems and components. In one embodiment, a parameterized model of a sub-component of an essentially digital system is provided....
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7120883 |
Register retiming technique
An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging...
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7120569 |
Sequential machine for solving boolean satisfiability (SAT) problems in linear time
The invention is a sequential machine for solving boolean satisfiability (SAT) problems for functions of n variables and m clauses in linear time with complexity O(m), independent of the number of...
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7120894 |
Pass-transistor logic circuit and a method of designing thereof
A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is...
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7117470 |
Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with...
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7117471 |
Generation of design views having consistent input/output pin definitions
Generation of consistent connection data for a first circuit embedded in a second circuit. In one approach, a master file is established with design data that includes for each pin in the embedded...
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7113655 |
Image processing apparatus
An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selector 52 selects one of the primitive data S 143 , the image...
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7114132 |
Device, system, server, client, and method for supporting component layout design on circuit board, and program for implementing the device
There is provided a circuit design supporting device, a circuit board design supporting system, a circuit board design supporting server, a circuit board design supporting client, a circuit design...
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7111269 |
Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout
A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the...
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7111275 |
Electronic circuit design analysis system
A method, apparatus and program product generate package files that are separately stored and selectively combined to generate a net file suited for system simulation and analysis. Selective...
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7111274 |
Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to...
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7111270 |
Method and apparatus to adaptively validate a physical net routing topology of a substrate design
A method and apparatus to adaptively validate a physical net routing topology of a substrate design to a target topology of the substrate design. A tree data structure is generated by mapping...
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7107567 |
Electronic design protection circuit
Protected electronic designs permit appropriate simulation and testing of the electronic design in a simulation environment, while preventing a correctly operating unauthorized implementation of...
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7107570 |
Method and system for user-defined triggering logic in a hardware description language
A method and system for user-defined triggering logic in a hardware description language is described. The method includes reading a file containing user-defined triggering logic described in a...
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7107566 |
Programmable logic device design tools with gate leakage reduction capabilities
Power consumption on programmable logic devices can be minimized by taking account of gate leakage effects. A logic design system may analyze a logic design to determine which signals are most...
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7107201 |
Simulating a logic design
Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for...
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7107569 |
Design method and apparatus for a semiconductor integrated circuit comprising checkers verifying the interface between circuit blocks
A functional block for verifying correct interface operation of any functional block is generated from interface description and installed on a LSI chip. To accomplish this, from the interface...
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7107568 |
System and method for reducing wire delay or congestion during synthesis of hardware solvers
One embodiment of the invention is a method for producing a hardware solver for intermediate code comprising analyzing intermediate code for at least one instantiation that may cause at least one...
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7103861 |
Test structure for automatic dynamic negative-bias temperature instability testing
The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI)....
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7103523 |
Method and apparatus for implementing multiple configurations of multiple IO subsystems in a single simulation model
A method and apparatus are provided for implementing multiple configurations of multiple input/output (IO) subsystems in a single simulation model. At least one bus routing switch is included in...
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7103859 |
System and method for improving testability independent of architecture
A testability analysis system analyzes testability by evaluating controllability and observability at the level of a hardware functional description independent of architecture. The testability...
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7103858 |
Process and apparatus for characterizing intellectual property for integration into an IC platform environment
A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration...
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7100141 |
Technology mapping technique for fracturable logic elements
A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design...
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7100143 |
Method and apparatus for pre-tabulating sub-networks
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
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7100142 |
Method and apparatus for creating a mask-programmable architecture from standard cells
One embodiment of the invention provides a system for creating a mask-programmable module from standard cells. The system operates by first specifying characteristics of an end design and then...
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7100144 |
System and method for topology selection to minimize leakage power during synthesis
A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further...
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7096174 |
Systems, methods and computer program products for creating hierarchical equivalent circuit models
Systems, methods and computer program products create an equivalent circuit of electric and/or electronic circuit components, by identifying groups of components and hierarchically modeling...
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7096447 |
Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout
An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair...
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7093224 |
Model-based logic design
A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data...
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7093204 |
Method and apparatus for automated synthesis of multi-channel circuits
Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and...
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7093213 |
Method for designing an integrated circuit defect monitor
A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed...
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7093208 |
Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner...
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7089511 |
Framework for hierarchical VLSI design
A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The...
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7086030 |
Incremental netlisting
Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a...
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7082584 |
Automated analysis of RTL code containing ASIC vendor rules
A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the...
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7082592 |
Method for programming programmable logic device having specialized functional blocks
A programming method efficiently programs programmable logic devices of the type having specialized functional blocks. Those blocks may include multipliers and other arithmetic function elements,...
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7082591 |
Method for effectively embedding various integrated circuits within field programmable gate arrays
A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a...
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7082595 |
Schematic driven placement method and program product for custom VLSI circuit design
A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition...
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7082593 |
Method and apparatus of IC implementation based on C++ language description
The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++...
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7082594 |
Compilation in a high-level modeling system
Methods and apparatus are disclosed for compiling high-level blocks of an electronic hardware design in a high-level modeling system (HLMS) into hardware description language (HDL) components....
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7079104 |
Semiconductor device and liquid crystal panel display driver
A semiconductor device that operates with reduced power consumption having a clock transfer blocking circuit and an external data transfer blocking circuit that blocks a clock signal and a data...
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