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7617472 |
Regional signal-distribution network for an integrated circuit
Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The...
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7617471 |
Processor event interface for programmable integrated circuit based circuit designs
A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A...
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7617470 |
Reconfigurable integrated circuit and method for increasing performance of a reconfigurable integrated circuit
Methods are disclosed to increase yielded performance of a reconfigurable integrated circuit; improve performance of an application running on a reconfigurable integrated circuit; reduce...
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7614027 |
Methods for forming a MRAM with non-orthogonal wiring
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be...
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7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits
Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured...
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7614020 |
Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems
A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns...
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7607117 |
Representing device layout using tree structure
Methods are described herein for using a tree structure representation for searching selected areas of a programmable device layout in order to determine the existing component configuration of a...
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7607005 |
Virtual hardware system with universal ports using FPGA
Particular implementations are particularly useful in providing a system in which the hardware is more easily upgradable and new hardware functionality may be added without adding any new physical...
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7603646 |
Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables
Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for...
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7603599 |
Method to test routed networks
Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources...
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7596775 |
Method for determining a standard cell for IC design
IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index)...
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7596774 |
Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
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7594211 |
Methods and apparatuses for reset conditioning in integrated circuits
Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred...
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7590965 |
Methods of generating a design architecture tailored to specified requirements of a PLD design
Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design...
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7590960 |
Placing partitioned circuit designs within iterative implementation flows
A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding...
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7590951 |
Plug-in component-based dependency management for partitions within an incremental implementation flow
A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and,...
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7587699 |
Automated system for designing and developing field programmable gate arrays
An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is...
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7587686 |
Clock gating in a structured ASIC
Circuits and methods use clock gating to reduce power consumption in select parts of a structured ASIC. A clock distribution network includes a deterministic portion, a configurable portion, and...
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7584447 |
PLD architecture for flexible placement of IP function blocks
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
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7574681 |
Method and system for evaluating computer program tests by means of mutation analysis
Methods and systems for evaluating computer program tests by mutation analysis, including the execution of mutated programs with the insertion of mutations and the identification of mutated...
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7574680 |
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory...
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7574679 |
Generating cores using secure scripts
Methods and apparatus are provided for securely generating IP cores. A designer selects and configures parameterizable IP cores provided for implementation on a programmable chip. The IP cores are...
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7571415 |
Layout of power device
A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The...
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7571414 |
Multi-project system-on-chip and its method
A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral...
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7571395 |
Generation of a circuit design from a command language specification of blocks in matrix form
Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands...
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7568172 |
Integration of pre-defined functionality and a graphical program in a circuit
System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in...
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7562332 |
Disabling unused/inactive resources in programmable logic devices for static power reduction
A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic...
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7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate
A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the...
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7562324 |
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew...
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7562162 |
Systems and methods for distributed computing utilizing a smart memory apparatus
Provided are methods, systems and devices for distributed computing within a computing device that includes a host operating system executing within a host processor, a peripheral subsystem and a...
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7559045 |
Database-aided circuit design system and method therefor
A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage...
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7558969 |
Anti-pirate circuit for protection against commercial integrated circuit pirates
Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that...
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7558967 |
Encryption for a stream file in an FPGA integrated circuit
A system for encrypting and decrypting data in a data stream for programming a Field Programmable Gate Array (FPGA). The system allows for an enable bit to be set for a gap in the data stream and...
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7549139 |
Tuning programmable logic devices for low-power design implementation
A method of operating a programmable logic device includes the steps of using a full V DD supply voltage to operate a first set of active blocks of the programmable logic device, and using a...
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7546570 |
Communications bus for a parallel processing system
A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting...
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7546556 |
Virtual shape based parameterized cell
A method of designing an electric circuit includes generating a part of the design, determining a virtual shape based on the part, and using the virtual shape to generate a design for an additional...
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7546394 |
Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems
Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of...
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7543283 |
Flexible instruction processor systems and methods
The present invention relates to the design-time and run-time environments of instruction processors implemented in re-programmable hardware. In one aspect the present invention provides a design...
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7543265 |
Method for early logic mapping during FPGA synthesis
Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping,...
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7539967 |
Self-configuring components on a device
Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter...
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7539953 |
Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system
Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is...
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7536669 |
Generic DMA IP core interface for FPGA platform design
A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as...
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7536668 |
Determining networks of a tile module of a programmable logic device
A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module...
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7536615 |
Logic analyzer systems and methods for programmable logic devices
A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for...
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7536289 |
Method of configuring information processing system and semiconductor integrated circuit
A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step...
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7533362 |
Allocating hardware resources for high-level language code sequences
Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level language are overloaded with information...
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7530047 |
Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the...
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7530046 |
Chip debugging using incremental recompilation
While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes...
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7530044 |
Method for manufacturing a programmable system in package
Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies several...
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7526745 |
Method for specification and integration of reusable IP constraints
A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode...
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