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6920626 Method for re-encoding a decoder  
A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making...
6915503 Methods of utilizing noise cores in PLD designs to facilitate future design modifications  
Methods of using “noise cores” in a PLD design. “Noise cores” are pre-developed blocks of logic included in a PLD design for the purpose of creating noise in other circuits also implemented...
6915251 Memories having reduced bitline voltage offsets  
A memory device design is provided. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline...
6912706 Instruction processor and programmable logic device cooperative computing arrangement and method  
A method and arrangement for executing instructions of a computer program using a programmable logic device to perform selected functions of the program. Profile data for code segments of the...
6912702 Non-linear, gain-based modeling of circuit delay for an electronic design automation system  
A non-linear, gain-based modeling of circuit delay within an electronic design automation system. The present invention provides a scalable cell model for use in early logic structuring and mapping...
6912703 Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation  
A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the...
6910201 Custom clock interconnects on a standardized silicon platform  
A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each...
6907595 Partial reconfiguration of a programmable logic device using an on-chip processor  
A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration...
6901563 Storing of global parameter defaults and using them over two or more design projects  
A system and method for graphically displaying global resources and their associated parameter values and apply the global resources across multiple design projects. The system and method also...
6901572 Power sequence controller programming technique  
A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user...
6897678 Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits  
A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device....
6898775 System for ensuring correct pin assignments between system board connections using common mapping files  
The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of...
6898776 Method for concurrently programming a plurality of in-system-programmable logic devices by grouping devices to achieve minimum configuration time  
A method for concurrently programming a series of in-system devices by grouping the devices into sequentially-programmed groups, wherein a best possible grouping of devices is determined that...
6892373 Integrated circuit cell library  
According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the...
6892370 Computerized standard cell library for designing integrated circuits (ICs) with high metal layer intra cell signal wiring, and ICs including same  
The present invention is for a computerized standard cell library with inter alia standard cells having high metal layer intra cell signal wiring for use in designing ICs in accordance with a...
6889368 Method and apparatus for localizing faults within a programmable logic device  
Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to...
6886150 Method for designing integrated circuit device  
Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable...
6886146 Method of bypassing a plurality of clock trees in EDA tools  
A method for using timing simulation and authentication software of an EDA tool (electronics design automatic tool) to bypass a plurality of clock trees in the EDA tool. The EDA tool contains a...
6886143 Method and apparatus for providing clock/buffer network in mask-programmable logic device  
A mask-programmable logic device includes a “dedicated” device-wide distribution network for device-wide signals such as clocks. Distribution networks for secondary clocks and similar signals,...
6886092 Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion  
A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code....
6883151 Method and device for IC identification  
The present invention provides a method for IC identification. It can be used to identify the origin of the IC design, wherein said IC comprises at least a testing circuit for testing the...
6880146 Molecular-wire-based restorative multiplexer, and method for constructing a multiplexer based on a configurable, molecular-junction-nanowire crossbar  
A method for configuring any m-to-n multiplexer from a molecular-junction-nanowire crossbar, and m-to-n multiplexers configured according to the disclosed method. In the described embodiments, a...
6877145 Automatic generation of interconnect logic components  
A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to...
6876962 Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system  
An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit...
6868374 Method of power distribution analysis for I/O circuits in ASIC designs  
A method and system for testing the compliance of a distribution of I/O circuits in a semiconductor chip with voltage (IR) and electromigration (EM) limits. Maximum and average currents for the I/O...
6865726 IC layout system employing a hierarchical database by updating cell library  
An IC layout system compiles a hierarchical netlist describing an IC into a database having a separate record for each cell and each module of the IC. Each database record references a cell library...
6862724 Reconfigurable programmable logic system with peripheral identification data  
A reconfigurable programmable logic system including a programmable logic device and an associated processor is configured using a configuration file including (a) instructions for configuring the...
6859917 Semiconductor integrated circuit having high-speed and low-power logic gates with common transistor substrate potentials, design methods thereof, and related program recording medium  
Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a...
6856951 Repartitioning performance estimation in a hardware-software system  
A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by...
6857110 Design methodology for merging programmable logic into a custom IC  
A programmable logic core (PLC) can be integrated into custom ICs such as ASICs and SOCs using a unique design methodology. For example, the methodology can incorporate the PLC into the entire ASIC...
6854096 Optimization of cell subtypes in a hierarchical design flow  
Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance...
6848095 Method of assigning logic functions to macrocells in a programmable logic device  
A method of assigning logic functions to macrocells assures that a maximum number of macrocells are assigned two or more logic functions. A first logic function is assigned to a macrocell without...
6845496 Semiconductor integrated circuit device using programmable peripheral control  
A programmable peripheral LSI contains a number of microprocessor peripheral IPs. A switch is provided for selectively disabling peripheral IPs. As a result, the peripheral IPs are disabled while...
6842888 Method and apparatus for hierarchically restructuring portions of a hierarchical database based on selected attributes  
A method and apparatus for hierarchically restructuring at least a portion of a hierarchical database based on selected attributes. In one embodiment, a virtual cell ( 140 ) may use a virtual cell...
6839882 Method and apparatus for design of integrated circuits  
Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments...
6839888 Method for implementing bit-swap functions in a field programmable gate array  
There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1)...
6834263 NROM structure  
A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped...
6832180 Method for reducing noise in integrated circuit layouts  
A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a...
6826741 Flexible I/O routing resources  
In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to...
6826732 Method, system and program product for utilizing a configuration database to configure a hardware digital system  
A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial...
6820248 Method and apparatus for routing interconnects to devices with dissimilar pitches  
Method for configuring a routing program for routing connections between an integrated circuit device and an embedded core is described. More particularly, horizontal and a vertical pitch are...
6816826 Fully exhibiting asynchronous behavior in a logic network simulation  
A logic network is simulated, including partitioning logic operations into domains and ranking the operations. Some operations are dependent on source operations from other domains. Pairs of...
6810514 Controller arrangement for partial reconfiguration of a programmable logic device  
Method and apparatus for partial reconfiguration of a programmable logic device (PLD). In one embodiment, a configuration store is arranged for storage of configuration data for a selected subset...
6807658 Systems and methods for performing clock gating checks  
A gating signal checker system and method are provided to perform clock gating check on a logic cell. In accordance with one aspect of the invention, the system includes logic that determines a...
6807653 Recovery path designing circuit, method and program thereof  
A recovery path designing circuit, a method and a program thereof capable of reducing necessary resources as much as possible when designing a recovery path in a pre-establishing-type...
6804812 Depopulated programmable logic array  
A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining...
6803782 Arrayed processing element redundancy architecture  
A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory...
6795960 Signal routing in programmable logic devices  
The present invention provides a new method to handle a signal that crosses one or more areas in modular design of programmable logic devices. Even when the signal have an attribute disallowing the...
6792584 System and method for designing an integrated circuit  
The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and...
6792578 Hard macro having an antenna rule violation free input/output ports  
Disclosed is an improved hard macro design for use in an ASIC, which avoids undesirable buildup of electrostatic charge on a gate of an I/O transistor of the hard macro. The hard macro includes a...
Matches 401 - 450 out of 801 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >