Matches 351 - 400 out of 801 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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7028274 RRAM backend flow  
A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is...
7028283 Method of using a hardware library in a programmable logic device  
A method of using hardware libraries in a programmable logic device is disclosed. In particular, the method generally comprises steps of detecting a hardware library when compiling a software...
7024654 System and method for configuring analog elements in a configurable hardware device  
A system is provided for programming a configurable semiconductor device. The system includes a programmable controlling device, a programmable computing device, a communication link, a...
7024641 Integrated circuit having a programmable gate array and a field programmable gate array and methods of designing and manufacturing the same using testing IC before configuring FPGA  
The present invention provides an integrated circuit (IC). In one embodiment, the IC includes a substrate and a plurality of gate array blocks located on the substrate. Each of the blocks includes...
7024653 Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)  
According to one embodiment, an integrated circuit ( 100 ) includes a programmable portion ( 102 ) and a communication portion ( 104 ). A programmable portion ( 102 ) may include logic circuits...
7024651 Partial reconfiguration of a programmable gate array using a bus macro  
A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed...
7020850 Event-based temporal logic  
A computer system receives a description of a finite state machine including a temporal logic condition and generates code for emulating the described finite state machine.
7020862 Circuits and methods for analyzing timing characteristics of sequential logic elements  
Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable...
7020864 Optimized technology mapping techniques for programmable circuits  
Technology mapping techniques are provided for converting a user design for a programmable integrated circuit to a network of programmable logic blocks. The technology mapping process attempts to...
7017136 Architecture and interconnect scheme for programmable logic circuits  
An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block...
7017140 Common components in interface framework for developing field programmable based applications independent of target circuit board  
A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD)....
7010772 Method and apparatus for generating superset pinout for devices with high-speed transceiver channels  
A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the...
7010773 Method for designing a circuit for programmable microcontrollers  
A method to program a microcontroller using a software program. First a user selects a module from a catalog of available modules. The module may be for implementing an amplifier, timer, pulse...
7010777 Shared lookup table enhancements for the efficient implementation of barrel shifters  
Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive...
7009421 Field programmable gate array core cell with efficient logic packing  
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA...
7007252 Method and apparatus for characterizing the propagation of noise through a cell in an integrated circuit  
One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the...
7003753 Method of generating a physical netlist for a hierarchical integrated circuit design  
A method of generating a physical netlist for an integrated circuit design includes steps of: (a) receiving as input a representation of a core cell for a hierarchical integrated circuit design;...
7003743 Method and system of data processor design by sensitizing logical difference  
A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test...
7003732 Method and system for data-driven display grids  
A method and system of automatically generating information in a grid structure on a display screen. In one embodiment, the present invention is directed to displaying and editing microcontroller...
7000212 Hierarchical general interconnect architecture for high density FPGA'S  
Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a hierarchical general interconnect architecture in which: (1) reliance on single-length general...
7000211 System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources  
A system and method of mapping heterogeneous objects onto an array of heterogeneous programmable logic resources. The method comprises clustering to identify datapath modules from a netlist. The...
7000090 Center focused single instruction multiple data (SIMD) array system  
A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of...
6993766 Integrated circuits for multi-tasking support in single or multiple processor networks  
An integrated circuit ( 7 A) for multitasking support for processing unit ( 1 A) holds control variables for each task (or activity) to run on its associated processor ( 1 A) and identifies the...
6988251 Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs  
A semiconductor device comprising one or more diffused memories and one or more diffused regions. The one or more diffused regions may be configured to provide one or more ports for the one or more...
6988258 Mask-programmable logic device with building block architecture  
A mask-programmable logic device includes logical building blocks that can be connected together to form various logical units for programmable logic. Functionality of a comparable conventional...
6985843 Cell modeling in the design of an integrated circuit  
The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is...
6983429 Formal proof methods for analyzing circuit loading problems under operating conditions  
A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a...
6983441 Embedding a JTAG host controller into an FPGA design  
A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary...
6981236 Method for modeling semiconductor device and network  
A method for modeling a device and a network to be analyzed in a complex simulation. The modeling method includes a device extraction step for extracting the structure of each of a plurality of...
6978435 Apparatus for programming a programmable device, and method  
An apparatus is provided for programming a programmable circuit device capable of realizing at least one sub-circuit by wiring together at least one circuit component. The programmable circuit...
6976239 Methods and apparatus for implementing parameterizable processors and peripherals  
Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization...
6973629 Circuit arrangement  
Fuses that selectively disable functional blocks of a circuit are arranged in a multistage structure, wherein if any fuse element in the multistage structure permanently switches off a part of the...
6970814 Remote IP simulation modeling  
A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit...
6965972 Real time emulation of coherence directories using global sparse directories  
A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache...
6966043 Method for designing minimal cost, timing correct hardware during circuit synthesis  
A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from...
6966044 Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources  
A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory...
6966039 Method for facilitating microcontroller programming  
A method to facilitate circuit design. First, a schematic and data sheet for a selected module may be displayed. Next, in response to a request for a position for the module among available...
6961919 Method of designing integrated circuit having both configurable and fixed logic circuitry  
A method for designing an integrated circuit having both fixed logic and programmable logic components. An intended set of applications for the integrated circuit is first identified. In addition,...
6960935 Method and apparatus for cascade programming a chain of cores in an embedded environment  
A system for clearing and programming the memory of an FPGA IC, when the IC is comprised of a plurality of cores. The system clears the memory of the of cores. The system then sequentially verifies...
6961917 Method for activating fuse units in electronic circuit device  
The invention provides a method for activating fuse units ( 101 a -101 n ) in an electronic circuit device ( 100 ) in order to modify a circuit design for the electronic circuit device ( 100 ),...
6950996 Interconnect delay and slew metrics based on the lognormal distribution  
A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a...
6948145 Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements  
A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool...
6947883 Method for designing mixed signal integrated circuits and configurable synchronous digital noise emulator circuit  
A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of...
6948147 Method and apparatus for configuring a programmable logic device using a master JTAG port  
Method and apparatus for configuring a programmable logic device using configuration data stored in an external memory is described. In an example, a boundary scan port includes a data input...
6944582 Methods for reducing bitline voltage offsets in memory devices  
A method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of...
6938236 Method of creating a mask-programmed logic device from a pre-existing circuit design  
A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file,...
6934925 Method for designing semiconductor circuit  
This invention provides a method for designing a semiconductor circuit which comprises a macro design step for designing plural macros in which plural cells are internally connected and a whole...
6934923 Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit  
A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of...
6934927 Turn architecture for routing resources in a field programmable gate array  
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery....
6922665 Method and system for device-level simulation of a circuit design for a programmable logic device  
A method and system for simulating a circuit design for a programmable logic device (PLD) at the device level. The same configuration data that is used to configure a PLD is used to generate...
Matches 351 - 400 out of 801 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >