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7318210 Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays  
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes placing new logic elements (LEs) at preferred locations on a layout of an existing...
7313778 Method system and apparatus for floorplanning programmable logic designs  
A method ( 600 ) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable...
7313775 Integrated circuit with relocatable processor hardmac  
An integrated circuit layout is provided, which includes a base platform for an integrated circuit, a processor hardmac and a support memory. The base platform includes a memory matrix having leaf...
7313768 Register file and method for designing a register file  
A register file includes a plurality of registers for storing therein data, a plurality of input ports for receiving therethrough the data to be stored in the registers, and a plurality of output...
7313730 Configuration logic for embedded software  
An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that...
7309908 Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device  
To prevent the potential inversion of a dynamic node attributed to the fact that any wiring line among standard cells as is made of a wiring layer at the same level as that of the dynamic node...
7310795 Method and apparatus for simulating logic circuits that include a circuit block to which power is not supplied  
A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which...
7308668 Apparatus and method for implementing an integrated circuit IP core library architecture  
An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner...
7308671 Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cells  
A method for designing a system on a field programmable gate array (FPGA) includes performing mapping with a plurality of passes where a different assumption is made with respect to a property of...
7305649 Automatic generation of a streaming processor circuit  
A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation...
7302663 Automatic antenna diode insertion for integrated circuits  
Automatic antenna diode insertion for integrated circuits is described. In an example, at least a portion of an integrated circuit is defined by a block of standard cells selected from a cell...
7299307 Analog I/O with digital signal processor array  
Embodiments of the present invention relate to a programmable logical semiconductor device which is tailored for implementing digital signal processing functions. The programmable logical...
7299444 Interface for pin swap information  
An electronic board design includes a programmable logic device (PLD) and involves optimizing the routing of traces to the pins of the device. A graphic utility of an electronic design automation...
7299203 Method for storing and shipping programmable ASSP devices  
A novel method for order processing, manufacturing and distributing integrated circuits (ICs) including the steps of: dry packing a plurality of programmable ICs and placing the dry packed...
7299445 Nonlinear receiver model for gate-level delay calculation  
A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions)....
7290240 Leveraging combinations of synthesis, placement and incremental optimizations  
Multiple optimization phases are combined to improve the performance and decrease the compilation time of user designs. An initial user design is compiled and analyzed to provide timing...
7290237 Method for programming a mask-programmable logic device and device so programmed  
A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be...
7290236 Configuration and/or reconfiguration of integrated circuit devices that include programmable logic and microprocessor circuitry  
An integrated circuit includes programmable logic circuitry and control circuitry that is operable to enable the integrated circuit to make a connection to an external source of data for...
7283946 Microcomputer logic development system  
Provided is a system for developing the preceding logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit. The system has a CPU whose...
7284226 Methods and structures of providing modular integrated circuits  
Modular wafers and integrated circuits (ICs), and methods of manufacturing modular ICs. A modular wafer can be optionally divided in various ways to avoid defects while producing a variety of...
7284229 Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein  
Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization...
7283943 Method of modeling circuit cells for powergrid analysis  
Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node...
7281228 Configurable memory system for embedded processors  
An embedded processor architecture includes a processing core with configurable memory system. Memory components can be inserted, omitted and resized in different configuration of the memory system...
7277902 Method and apparatus for comparing and synchronizing programmable logic device user configuration dataset versions  
A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e.g., the user...
7278128 Method of altering a bitstream  
A method is disclosed for redeploying an FPGA that has been restricted for use with a first design. The FPGA accepts only those configuration bitstreams whose CRC checksums match a value stored on...
7272812 Semiconductor designing apparatus using sub-circuit recognizer  
A semiconductor designing apparatus capable of effectively performing a layout designing operation and capable of developing both a circuit designing operation and a layout designing operation at...
7272814 Reconfiguring a RAM to a ROM using layers of metallization  
The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect...
7272804 Generation of RTL to carry out parallel arithmetic operations  
Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be...
7269814 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA  
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA...
7266795 System and method for engine-controlled case splitting within multiple-engine based verification framework  
A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of...
7263565 Bus system and integrated circuit having an address monitor unit  
A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared...
7263478 System and method for design verification  
An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility...
7263456 On circuit finalization of configuration data in a reconfigurable circuit  
Reconfigurable circuits with configuration data loaders are described herein. The configuration data loaders are adapted to enable on circuit finalization of configuration data provided in symbolic...
7263681 Semiconductor integrated circuit device and layout method of patterns for semiconductor integrated circuit device  
A semiconductor integrated circuit device includes macros and area I/Os. The macros are arranged in optional locations of a first empty area of a gate area in a center portion of a chip,...
7260807 Method and apparatus for designing an integrated circuit using a mask-programmable fabric  
One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a...
7257801 Cell library database and timing verification and withstand voltage verification systems for integrated circuit using the same  
In a cell library database, timing verification is conducted on an LSI which exists in a variable power supply system capable of changing the source voltage arbitrarily and which includes logic...
7257795 Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints  
Methods and apparatuses are disclosed to facilitate routing between a first and second component in a programmable logic device to generate a path with an appropriate amount of delay to satisfy...
7257803 Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith  
Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language...
7254801 Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis  
A system and method improves the effectiveness of logic duplication optimizations by dynamically allocating the usage of logic duplicates. Duplicate atoms in the user design are identified. Atoms...
7251805 ASICs having more features than generally usable at one time and methods of use  
More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive...
7251792 Net list creating method, net list creating device, and computer program thereof  
It is intended to provide net list creating method, net list creating device, and computer program thereof capable of creating net list of memory space by selecting optimum combination of memory...
7251804 Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof  
Methods of programming an integrated circuit (IC) such as a programmable logic device to avoid localized defects present in the IC, and ICs capable of performing these methods. As part of an...
7249339 Method and apparatus for optimizing delay paths through field programmable gate arrays  
A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and...
7249340 Adaptable circuit blocks for use in multi-block chip design  
Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component...
7243329 Application-specific integrated circuit equivalents of programmable logic and associated methods  
Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each...
7243330 Method and apparatus for providing self-implementing hardware-software libraries  
Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A...
7243315 Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays  
As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been...
7240320 Routing with derivative frame awareness to minimize device programming time and test cost  
A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD...
7234125 Timing analysis for programmable logic  
Programming software for mask-programmable logic devices provides a timing estimation to the user for the user's logic design during the compilation stage, notwithstanding that the software is not...
7234127 Integrated circuit designing support apparatus and method for the same  
An integrated circuit designing support apparatus includes a storage unit and a processing unit. The storage unit stores an RTL (Register Transfer Level) description with description of...
Matches 201 - 250 out of 800 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >