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7546394 |
Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems
Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of...
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7546556 |
Virtual shape based parameterized cell
A method of designing an electric circuit includes generating a part of the design, determining a virtual shape based on the part, and using the virtual shape to generate a design for an additional...
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7546570 |
Communications bus for a parallel processing system
A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting...
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7543265 |
Method for early logic mapping during FPGA synthesis
Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping,...
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7543283 |
Flexible instruction processor systems and methods
The present invention relates to the design-time and run-time environments of instruction processors implemented in re-programmable hardware. In one aspect the present invention provides a design...
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7539953 |
Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system
Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is...
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7539967 |
Self-configuring components on a device
Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter...
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7536668 |
Determining networks of a tile module of a programmable logic device
A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module...
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7536289 |
Method of configuring information processing system and semiconductor integrated circuit
A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step...
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7536669 |
Generic DMA IP core interface for FPGA platform design
A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as...
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7536615 |
Logic analyzer systems and methods for programmable logic devices
A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for...
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7533362 |
Allocating hardware resources for high-level language code sequences
Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level language are overloaded with information...
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7530046 |
Chip debugging using incremental recompilation
While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes...
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7530044 |
Method for manufacturing a programmable system in package
Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies several...
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7530047 |
Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the...
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7526745 |
Method for specification and integration of reusable IP constraints
A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode...
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7523434 |
Interfacing with a dynamically configurable arithmetic unit
An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for...
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7523430 |
Programmable logic device design tool with simultaneous switching noise awareness
A logic design system is provided for designing programmable logic device integrated circuits with minimized simultaneous switching noise. The logic design system identifies input-output drivers...
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7519823 |
Concealed, non-intrusive watermarks for configuration bitstreams
Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration...
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7516436 |
Method for manufacturing a power bus on a chip
A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a...
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7512922 |
Methods of structured placement of a circuit design
A method of creating relatively placed macros (RPMS) for a circuit design for a target device can include determining N best configurations for each of a plurality of connections of the circuit...
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7512917 |
Method for verifying safety apparatus and safety apparatus verified by the same
A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of...
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7512850 |
Checkpointing user design states in a configurable IC
Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values....
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7509547 |
System and method for testing of interconnects in a programmable logic device
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the...
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7509610 |
Timing analysis for programmable logic devices fabricated in different Fabs
Timing analysis of integrated circuits fabricated in different Fabs is described. A first speed file and a second speed file for a type of integrated circuit respectively fabricated in a first Fab...
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7506297 |
Methodology for scheduling, partitioning and mapping computational tasks onto scalable, high performance, hybrid FPGA networks
An automatically reconfigurable high performance FPGA system that includes a hybrid FPGA network and an automated scheduling, partitioning and mapping software tool adapted to configure the hybrid...
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7506296 |
Programmable logic device design tool with support for variable predriver power supply levels
A logic design system is provided for designing programmable logic device integrated circuits with minimized predriver power consumption. The logic design system identifies predriver circuits that...
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7503017 |
Method and program for library generation
A library generation device determines a characteristic approximation function based on a characteristic extraction table to calculate characteristic data corresponding to a client's conditions in...
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7500215 |
Method of developing application-specific integrated circuit devices
A method, computer readable medium apparatus and system for developing an Application-Specific Integrated Circuit (“ASIC”) are disclosed. In one embodiment, a method includes defining the...
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7500213 |
Array-based architecture for molecular electronics
An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are...
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7500214 |
System and method for reducing design cycle time for designing input/output cells
I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be...
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7498840 |
Reconfigurable integrated circuits with scalable architecture including one or more adders
An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or...
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7500162 |
Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing
An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input...
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7496879 |
Concurrent optimization of physical design and operational cycle assignment
Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for...
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7496820 |
Method and apparatus for generating test vectors for an integrated circuit under test
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one...
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7492184 |
Programmable logic device and method for designing the same
The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical...
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7493434 |
Determining the value of internal signals in a malfunctioning integrated circuit
A method that enables testing any point (target point) within a core, including a point within a combinatorial circuit of a core, permits testing of points that are not otherwise unobservable in...
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7487477 |
Parametric-based semiconductor design
A parametric-based design methodology interlocks the design of library elements used in a semiconductor product design with the testing protocol used for the resulting semiconductor products such...
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7480876 |
Method and software tool for designing an integrated circuit
A method of designing an integrated circuit for an application having standards having a plurality of primitives, each of the primitives having a corresponding response. The method includes...
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7478359 |
Formation of columnar application specific circuitry using a columnar programmable logic device
A columnar programmable logic device (PLD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PLD having...
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7478357 |
Versatile bus interface macro for dynamically reconfigurable designs
Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable...
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7478356 |
Timing driven logic block configuration
A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can...
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7478227 |
Apparatus and method for optimizing loop buffer in reconfigurable processor
A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating...
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7478355 |
Input/output circuits with programmable option and related method
A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a...
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7478358 |
Semiconductor integrated circuit device
LSI device 100 is provided with standard cell regions 10 , a plurality of standard cells 20 , memory blocks 11 and a plurality of memory cells 21 . Standard cells 20 are equal in height...
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7472369 |
Embedding identification information on programmable devices
Methods and apparatus are provided for embedding identification information on a programmable chip. Parameterizable components are selected for implementation on a programmable chip. Information...
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7472370 |
Comparing graphical and netlist connections of a programmable logic device
A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD...
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7472358 |
Method and system for outputting a sequence of commands and data described by a flowchart
The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of...
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7469261 |
Apparatus and method for protecting system data on computer hard-disk
An apparatus and method for protecting and recovering system data stored in a computer hard disk from corruption that may occur due to malicious or accidental operation during use of a computer are...
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7469390 |
Method and software tool for automatic generation of software for integrated circuit processors
A method of generating software code for a processor of an IC based on a simple input description of the IC's standards. The method includes generating a macros description of each of the...
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